[PATCH] D117538: [RISCV] Add instruction schedule for Zbc extension and Zbs extension

[Ben Shi via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5ceb4f5446f3: [RISCV] Add instruction schedule for Zbc extension and Zbs extension (authored by Lian Wang <Lian.Wang at streamcomputing.com>, committed by benshi001).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117538/new/

https://reviews.llvm.org/D117538

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSchedRocket.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleB.td

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