[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4106
+        SDValue ExtractBitIdx;
+        uint64_t MaxEEW = Subtarget.getMaxELENForFixedLengthVectors();
+        MVT LargestEltVT = MVT::getIntegerVT(
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craig.topper wrote:
> Use `unsigned`. Nothing here needs 64-bits.
Done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389