[PATCH] D117385: [RISCV] Add patterns for vector widening integer multiply

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:600
+                                   "PseudoVWMULU">;
+defm : VPatWidenBinarySDNode_VV_VX<mul, zext_oneuse, anyext_oneuse,
+                                   "PseudoVWMULU">;
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You don't need to handle both orders or zext/anyext. Tablegen knows mul is commutable and will autogenerate the swapped version. Sorry I suspected you might not know that and should have mentioned it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117385/new/

https://reviews.llvm.org/D117385