[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4127
+        }
+        // We will use vmv.x.s to extract the elment to GPR, and if eew is less
+        // than XLEN, the value will be signed extend.
----------------
craig.topper wrote:
> elment -> element
Done.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4131
+        // GPR bit    | XLEN -1 |--------------| 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+        // mask index |    7    |--------------| 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+        // So if we want to extract the 7th element, we should set extract bit
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craig.topper wrote:
> Sign extend means that bit 7 and above all have the same value. So why can't we just check bit 7?
Done.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4112
+        } else {
+          WideEleVT = XLenVT;
+          WidenVecLen = Nums / XLenVT.getScalarSizeInBits();
----------------
craig.topper wrote:
> jacquesguan wrote:
> > craig.topper wrote:
> > > This won't work with Zve32 on RV64. A vector XLen elements wouldn't be legal.
> > I add `MaxEEW` to get the right largest vector element width that we could have on current target, but we do not support `Zve` extension now, so I just set it to 64 and add a `TODO` to  remind changing it after having `Zve`.
> You don't need Zve to test this. Before Zve was added to the spec we added a command line option "-riscv-v-fixed-length-vector-elen-max" to clip the ELEN.
Done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389