[PATCH] D76445: [WIP][RISCV][GlobalISel] Select ALU GPR instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.
Herald added subscribers: alextsao1999, eopXD.


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Comment at: llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp:97-108
+const TargetRegisterClass *
+RISCVInstructionSelector::getRegClass(Register Reg,
+                                      const MachineRegisterInfo &MRI) const {
+  const LLT Ty = MRI.getType(Reg);
+  const unsigned Size = Ty.getSizeInBits();
+
+  if (isRegInGprBank(Reg, MRI)) {
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This function name is misleading. Can you restructure to use something more like getRegClassForTypeOnBank (which AArch64 has a FIXME to make a generic TargetRegisterInfo method)


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https://reviews.llvm.org/D76445