[PATCH] D117508: [SDAG] add demanded bits transform for bswap

Mon Jan 17 13:13:48 PST 2022

spatel planned changes to this revision.
spatel marked an inline comment as done.
spatel added a comment.

Just noticed that MSP430 can infinite loop because it doesn't have legal shifts. This needs a legal op check to be safe.

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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1828
+      EVT ShAmtTy = VT;
+      if (TLO.LegalTypes() && !ShAmtTy.isVector())
+        ShAmtTy = getShiftAmountTy(ShAmtTy, DL);
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craig.topper wrote:
> Why can't we use getShiftAmountTy always? I fixed the problem that it only works for legal types a few months ago.
Ah, didn't realize that. I copied this from the `case ISD::SIGN_EXTEND_INREG` block (line 1876). I can update that as a cleanup.

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  https://reviews.llvm.org/D117508/new/

https://reviews.llvm.org/D117508