[PATCH] D117454: [RISCV] Add patterns for vector narrowing integer right shift instructions

[Yueh-Ting Chen via Phabricator via llvm-commits]

eopXD updated this revision to Diff 400600.
eopXD added a comment.

Update code: rewrite to VLMax


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117454/new/

https://reviews.llvm.org/D117454

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

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