[PATCH] D86578: [TargetLowering] Combine known bits for icmp in SimplifySetCC (PR41182)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 400593.
RKSimon edited the summary of this revision.
RKSimon added a comment.
Herald added subscribers: kerbowa, javed.absar, nhaehnle, jvesely.

Updated the old patch to use the KnownBits comparison helpers that have been added since the original patch was created and add all test changes for review.

I've removed the branch removal code for now - which means we have a number of "constant" conditional branches that we currently have no way to fold to a jump, whatever we go for here handling this in the DAG would be rather ugly.

I'm open to suggestions for any individual test changes - some are definite improvements, some just need some tweaking and others probably affect the original regression the test was reduced from.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86578/new/

https://reviews.llvm.org/D86578

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll
  llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
  llvm/test/CodeGen/AMDGPU/wave32.ll
  llvm/test/CodeGen/ARM/bfi.ll
  llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
  llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
  llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/cmp.ll
  llvm/test/CodeGen/X86/fold-rmw-ops.ll
  llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
  llvm/test/CodeGen/X86/or-with-overflow.ll
  llvm/test/CodeGen/X86/pr16031.ll
  llvm/test/CodeGen/X86/scheduler-backtracking.ll
  llvm/test/CodeGen/X86/shrink-compare-pgso.ll
  llvm/test/CodeGen/X86/shrink-compare.ll
  llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll

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