[PATCH] D117429: [AArch64] Revive optimize add/sub with immediate through MIPeepholeOpt

Mon Jan 17 06:34:16 PST 2022

red1bluelost added a comment.

In D117429#3248191 <https://reviews.llvm.org/D117429#3248191>, @dmgreen wrote:

>> I don't think it is the same as visitORR. If you meant visitAND, I just checked an they are very similar expect differences where AND uses `splitBitmaskImm` while ADDSUB uses `splitAndSubImm`. Also the building of the ADDSUB MI's has an additional immediate for the shift value.
>
> Oh yeah. I meant the replaceRegWith etc at the end of visitAND (or visitORR). The way we update the operands is similar to something that we know has worked in the past, which is always a good sign.
>
> I can commit this, I just need a name/email to attribute it to. Is your @gmail account OK for that?

Yep, it was the `replaceRegWith` that fixed the second stage.

Here is name and email:
Micah Weston
micahsweston at gmail.com

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117429/new/

https://reviews.llvm.org/D117429