[PATCH] D115419: [PowerPC] Allow absolute expressions in relocations

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

In D115419#3247286 <https://reviews.llvm.org/D115419#3247286>, @shchenz wrote:

> Maybe I am misunderstanding the relocation fixups and DQ form instructions, if so, please ignore my comments. : )

For details of how this stuff works (i.e. constraints on relocations) please see section **3.5.1 Relocation Fields** of the ELF V2 ABI Specification.



================
Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp:47
   case PPC::fixup_ppc_half16ds:
+  case PPC::fixup_ppc_half16dq:
     return Value & 0xfffc;
----------------
shchenz wrote:
> For DQ form the adjusted value should be `Value & 0xfff0`? The last 4 bits are 0?
No, these two are the exact same thing, we just need to differentiate them by name. This is only to differentiate the two when we need to compute and validate the relocations (see the code in PPCMCExpr.cpp).


================
Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h:54
 
+  /// A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for
+  /// instrs like 'lxv'. Produces the same relocation as fixup_ppc_half16ds.
----------------
shchenz wrote:
> For DQ form, the fixup(DQ field?) should be 12 bits and 4 implied zero bits?
Oh, for the fixup, it should just be 2 bits (i.e. this is the exact same thing as the ds fixup).


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