[PATCH] D117465: [RISCV] Add patterns to MIR sign-extension removal pass.

[Mohammed Nurul Hoque via Phabricator via llvm-commits]

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This patch adds a few instruction patterns that generate sign-extended values or propagate them, adding to the pass introduced in https://reviews.llvm.org/D116397


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117465

Files:
  llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp


Index: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -95,10 +95,24 @@
   case RISCV::LHU:
   case RISCV::LB:
   case RISCV::LH:
+  case RISCV::SLT:
+  case RISCV::SLTI:
+  case RISCV::SLTU:
+  case RISCV::SLTIU:
   case RISCV::SEXTB:
   case RISCV::SEXTH:
   case RISCV::ZEXTH_RV64:
     return true;
+  // shifting right sufficiently makes the value 32-bit sign-extended
+  case RISCV::SRAI:
+    return MI.getOperand(2).getImm() >= 32;
+  case RISCV::SRLI:
+    return MI.getOperand(2).getImm() > 32;
+  // mask sets or resets bits 63:31
+  case RISCV::ANDI:
+    return countLeadingZeros((uint64_t)MI.getOperand(2).getImm()) > 32;
+  case RISCV::ORI:
+    return countLeadingOnes((uint64_t)MI.getOperand(2).getImm()) > 32;
   }
 
   // The LI pattern ADDI rd, X0, imm is sign extended.
@@ -157,9 +171,15 @@
       Worklist.push_back(SrcMI);
       break;
     }
+    case RISCV::DIVU:
+    case RISCV::REM:
+    case RISCV::REMU:
     case RISCV::ANDI:
     case RISCV::ORI:
     case RISCV::XORI: {
+      // |Quotient| and |Remainder| are always <= |Dividend|. If D fits in
+      // 32-bit, then so do Q & R. Sign-division doesn't work because of
+      // the edge case (long)0x8000 0000 / (long)-1
       // Logical operations use a sign extended 12-bit immediate. We just need
       // to check if the other operand is sign extended.
       Register SrcReg = MI->getOperand(1).getReg();


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