[llvm] 85def34 - [RISCV] Add scheduler for bfp instruction in Zbf extension
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 17 01:17:30 PST 2022
Author: Lian Wang
Date: 2022-01-17T09:17:18Z
New Revision: 85def34f5e450ed1d7cb0f3af8c74f89fe4c8d1d
URL: https://github.com/llvm/llvm-project/commit/85def34f5e450ed1d7cb0f3af8c74f89fe4c8d1d
DIFF: https://github.com/llvm/llvm-project/commit/85def34f5e450ed1d7cb0f3af8c74f89fe4c8d1d.diff
LOG: [RISCV] Add scheduler for bfp instruction in Zbf extension
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117290
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/lib/Target/RISCV/RISCVSchedRocket.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVScheduleB.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 3a0b5a5b694c..df39fbe0ddc7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -472,7 +472,8 @@ def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
} // Predicates = [HasStdExtZbm, IsRV64]
let Predicates = [HasStdExtZbf] in
-def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
+def BFP : ALU_rr<0b0100100, 0b111, "bfp">,
+ Sched<[WriteBFP, ReadBFP, ReadBFP]>;
let Predicates = [HasStdExtZbp] in {
def SHFLI : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
@@ -553,7 +554,8 @@ def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
} // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbf, IsRV64] in
-def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>;
+def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">,
+ Sched<[WriteBFP32, ReadBFP32, ReadBFP32]>;
let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index d5a0932c8778..ed9236e5c73f 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -237,5 +237,6 @@ def : ReadAdvance<ReadFClass64, 0>;
defm : UnsupportedSchedV;
defm : UnsupportedSchedZba;
defm : UnsupportedSchedZbb;
+defm : UnsupportedSchedZbf;
defm : UnsupportedSchedZfh;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 7f9d0aabc4ed..902653f94650 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -224,5 +224,6 @@ def : ReadAdvance<ReadFClass64, 0>;
defm : UnsupportedSchedV;
defm : UnsupportedSchedZba;
defm : UnsupportedSchedZbb;
+defm : UnsupportedSchedZbf;
defm : UnsupportedSchedZfh;
}
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleB.td b/llvm/lib/Target/RISCV/RISCVScheduleB.td
index b668b0acd719..6a69ceb65bea 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleB.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleB.td
@@ -26,6 +26,10 @@ def WriteCPOP32 : SchedWrite;
def WriteREV8 : SchedWrite;
def WriteORCB : SchedWrite;
+// Zbf extension
+def WriteBFP : SchedWrite; // BFP
+def WriteBFP32 : SchedWrite; // BFPW
+
/// Define scheduler resources associated with use operands.
// Zba extension
@@ -46,6 +50,10 @@ def ReadCPOP32 : SchedRead;
def ReadREV8 : SchedRead;
def ReadORCB : SchedRead;
+// Zbf extension
+def ReadBFP : SchedRead; // BFP
+def ReadBFP32 : SchedRead; // BFPW
+
/// Define default scheduler resources for B.
multiclass UnsupportedSchedZba {
@@ -87,3 +95,13 @@ def : ReadAdvance<ReadREV8, 0>;
def : ReadAdvance<ReadORCB, 0>;
}
}
+
+multiclass UnsupportedSchedZbf {
+let Unsupported = true in {
+def : WriteRes<WriteBFP, []>;
+def : WriteRes<WriteBFP32, []>;
+
+def : ReadAdvance<ReadBFP, 0>;
+def : ReadAdvance<ReadBFP32, 0>;
+}
+}
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