[PATCH] D117721: [AMDGPU] Make v8i16/v8f16 legal

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 19 16:22:53 PST 2022


rampitec added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll:1273-1282
+; GFX9-NEXT:    v_and_b32_e32 v0, v0, v4
+; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
+; GFX9-NEXT:    v_lshl_or_b32 v2, v2, 16, v1
+; GFX9-NEXT:    v_lshl_or_b32 v5, v5, 16, v3
+; GFX9-NEXT:    v_lshl_or_b32 v4, v4, 16, v0
+; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
----------------
rampitec wrote:
> arsenm wrote:
> > rampitec wrote:
> > > arsenm wrote:
> > > > What happened here?
> > > I believe this is the result of extract_subvector inserted by the extract_elt lowering for v8f16.
> > There's some special casing of other f16 vectors in LowerEXTRACT_SUBVECTOR which I would assume would follow for these
> Thanks, found it. I will probably need to add special cases for v8 too.
Hm... I run into the dag lowering loop. Maybe I need to find another way to do extract_elt here, w/o extract_subvector.


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  https://reviews.llvm.org/D117721/new/

https://reviews.llvm.org/D117721



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