[llvm] bf039a8 - [Target] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 23 22:53:29 PST 2022
Author: Kazu Hirata
Date: 2022-01-23T22:53:15-08:00
New Revision: bf039a8620f1779d02280cb0a33c4d818073623b
URL: https://github.com/llvm/llvm-project/commit/bf039a8620f1779d02280cb0a33c4d818073623b
DIFF: https://github.com/llvm/llvm-project/commit/bf039a8620f1779d02280cb0a33c4d818073623b.diff
LOG: [Target] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
llvm/lib/Target/VE/LVLGen.cpp
llvm/lib/Target/VE/VEMCInstLower.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86PadShortFunction.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp b/llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
index fc0d5cc6fbfa8..eeedce2d99cb0 100644
--- a/llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
@@ -57,12 +57,9 @@ bool NVPTXImageOptimizer::runOnFunction(Function &F) {
InstrToDelete.clear();
// Look for call instructions in the function
- for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE;
- ++BI) {
- for (BasicBlock::iterator I = (*BI).begin(), E = (*BI).end();
- I != E; ++I) {
- Instruction &Instr = *I;
- if (CallInst *CI = dyn_cast<CallInst>(I)) {
+ for (BasicBlock &BB : F) {
+ for (Instruction &Instr : BB) {
+ if (CallInst *CI = dyn_cast<CallInst>(&Instr)) {
Function *CalledF = CI->getCalledFunction();
if (CalledF && CalledF->isIntrinsic()) {
// This is an intrinsic function call, check if its an istypep
@@ -84,8 +81,8 @@ bool NVPTXImageOptimizer::runOnFunction(Function &F) {
}
// Delete any istypep instances we replaced in the IR
- for (unsigned i = 0, e = InstrToDelete.size(); i != e; ++i)
- InstrToDelete[i]->eraseFromParent();
+ for (Instruction *I : InstrToDelete)
+ I->eraseFromParent();
return Changed;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp b/llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp
index 6cf59d285e8d3..f655f25602bc3 100644
--- a/llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp
@@ -66,10 +66,9 @@ bool NVPTXLowerAggrCopies::runOnFunction(Function &F) {
getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
// Collect all aggregate loads and mem* calls.
- for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI) {
- for (BasicBlock::iterator II = BI->begin(), IE = BI->end(); II != IE;
- ++II) {
- if (LoadInst *LI = dyn_cast<LoadInst>(II)) {
+ for (BasicBlock &BB : F) {
+ for (Instruction &I : BB) {
+ if (LoadInst *LI = dyn_cast<LoadInst>(&I)) {
if (!LI->hasOneUse())
continue;
@@ -81,7 +80,7 @@ bool NVPTXLowerAggrCopies::runOnFunction(Function &F) {
continue;
AggrLoads.push_back(LI);
}
- } else if (MemIntrinsic *IntrCall = dyn_cast<MemIntrinsic>(II)) {
+ } else if (MemIntrinsic *IntrCall = dyn_cast<MemIntrinsic>(&I)) {
// Convert intrinsic calls with variable size or with constant size
// larger than the MaxAggrCopySize threshold.
if (ConstantInt *LenCI = dyn_cast<ConstantInt>(IntrCall->getLength())) {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 7edec82c6e067..eada872c2a7db 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2339,9 +2339,8 @@ bool PPCInstrInfo::ClobbersPredicate(MachineInstr &MI,
Found = true;
}
} else if (MO.isRegMask()) {
- for (TargetRegisterClass::iterator I = RC->begin(),
- IE = RC->end(); I != IE; ++I)
- if (MO.clobbersPhysReg(*I)) {
+ for (MCPhysReg R : *RC)
+ if (MO.clobbersPhysReg(R)) {
Pred.push_back(MO);
Found = true;
}
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 0c920582843ad..e5fa02bc8ccf0 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -258,12 +258,12 @@ void PPCMIPeephole::UpdateTOCSaves(
}
bool Keep = true;
- for (auto It = TOCSaves.begin(); It != TOCSaves.end(); It++ ) {
- MachineInstr *CurrInst = It->first;
+ for (auto &I : TOCSaves) {
+ MachineInstr *CurrInst = I.first;
// If new instruction dominates an existing one, mark existing one as
// redundant.
- if (It->second && MDT->dominates(MI, CurrInst))
- It->second = false;
+ if (I.second && MDT->dominates(MI, CurrInst))
+ I.second = false;
// Check if the new instruction is redundant.
if (MDT->dominates(CurrInst, MI)) {
Keep = false;
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index 707c1396e5728..cc5738a5d7b63 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -374,11 +374,10 @@ bool PPCTTIImpl::mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo,
// clobbers ctr.
auto asmClobbersCTR = [](InlineAsm *IA) {
InlineAsm::ConstraintInfoVector CIV = IA->ParseConstraints();
- for (unsigned i = 0, ie = CIV.size(); i < ie; ++i) {
- InlineAsm::ConstraintInfo &C = CIV[i];
+ for (const InlineAsm::ConstraintInfo &C : CIV) {
if (C.Type != InlineAsm::isInput)
- for (unsigned j = 0, je = C.Codes.size(); j < je; ++j)
- if (StringRef(C.Codes[j]).equals_insensitive("{ctr}"))
+ for (const auto &Code : C.Codes)
+ if (StringRef(Code).equals_insensitive("{ctr}"))
return true;
}
return false;
@@ -1301,8 +1300,8 @@ bool PPCTTIImpl::canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE,
LoopInfo *LI, DominatorTree *DT,
AssumptionCache *AC, TargetLibraryInfo *LibInfo) {
// Process nested loops first.
- for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I)
- if (canSaveCmp(*I, BI, SE, LI, DT, AC, LibInfo))
+ for (Loop *I : *L)
+ if (canSaveCmp(I, BI, SE, LI, DT, AC, LibInfo))
return false; // Stop search.
HardwareLoopInfo HWLoopInfo(L);
diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
index 0be35adc35c72..8a7d324ddfe15 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
@@ -297,18 +297,16 @@ namespace {
// fma result.
LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg);
- for (LiveInterval::iterator AI = FMAInt.begin(), AE = FMAInt.end();
- AI != AE; ++AI) {
+ for (auto &AI : FMAInt) {
// Don't add the segment that corresponds to the original copy.
- if (AI->valno == AddendValNo)
+ if (AI.valno == AddendValNo)
continue;
VNInfo *NewFMAValNo =
- NewFMAInt.getNextValue(AI->start,
- LIS->getVNInfoAllocator());
+ NewFMAInt.getNextValue(AI.start, LIS->getVNInfoAllocator());
- NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end,
- NewFMAValNo));
+ NewFMAInt.addSegment(
+ LiveInterval::Segment(AI.start, AI.end, NewFMAValNo));
}
LLVM_DEBUG(dbgs() << " extended: " << NewFMAInt << '\n');
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 881346bbe47ed..f10651d5c5d7e 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -8314,13 +8314,11 @@ MachineBasicBlock *SystemZTargetLowering::emitTransactionBegin(
// Add FPR/VR clobbers.
if (!NoFloat && (Control & 4) != 0) {
if (Subtarget.hasVector()) {
- for (int I = 0; I < 32; I++) {
- unsigned Reg = SystemZMC::VR128Regs[I];
+ for (unsigned Reg : SystemZMC::VR128Regs) {
MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
}
} else {
- for (int I = 0; I < 16; I++) {
- unsigned Reg = SystemZMC::FP64Regs[I];
+ for (unsigned Reg : SystemZMC::FP64Regs) {
MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
}
}
diff --git a/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp b/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
index 4b95d0d67389d..5a2cfc53da494 100644
--- a/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
@@ -170,15 +170,15 @@ bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
MF.insert(std::next(MachineFunction::iterator(MBB)), RestMBB);
RestMBB->splice(RestMBB->begin(), &MBB, MI, MBB.end());
RestMBB->transferSuccessors(&MBB);
- for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
- RestMBB->addLiveIn(*I);
+ for (MCPhysReg R : LiveRegs)
+ RestMBB->addLiveIn(R);
// Create a new block MoveMBB to hold the move instruction.
MachineBasicBlock *MoveMBB = MF.CreateMachineBasicBlock(BB);
MF.insert(std::next(MachineFunction::iterator(MBB)), MoveMBB);
MoveMBB->addLiveIn(SrcReg);
- for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
- MoveMBB->addLiveIn(*I);
+ for (MCPhysReg R : LiveRegs)
+ MoveMBB->addLiveIn(R);
// At the end of MBB, create a conditional branch to RestMBB if the
// condition is false, otherwise fall through to MoveMBB.
diff --git a/llvm/lib/Target/VE/LVLGen.cpp b/llvm/lib/Target/VE/LVLGen.cpp
index c4588926af9ed..4db6a59284c27 100644
--- a/llvm/lib/Target/VE/LVLGen.cpp
+++ b/llvm/lib/Target/VE/LVLGen.cpp
@@ -125,8 +125,8 @@ bool LVLGen::runOnMachineFunction(MachineFunction &F) {
TII = Subtarget.getInstrInfo();
TRI = Subtarget.getRegisterInfo();
- for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
- Changed |= runOnMachineBasicBlock(*FI);
+ for (MachineBasicBlock &MBB : F)
+ Changed |= runOnMachineBasicBlock(MBB);
if (Changed) {
LLVM_DEBUG(dbgs() << "\n");
diff --git a/llvm/lib/Target/VE/VEMCInstLower.cpp b/llvm/lib/Target/VE/VEMCInstLower.cpp
index bc5577ce4f978..57195f238cf6e 100644
--- a/llvm/lib/Target/VE/VEMCInstLower.cpp
+++ b/llvm/lib/Target/VE/VEMCInstLower.cpp
@@ -78,8 +78,7 @@ void llvm::LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP) {
OutMI.setOpcode(MI->getOpcode());
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
MCOperand MCOp = LowerOperand(MI, MO, AP);
if (MCOp.isValid())
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index 9da0a8129f230..4440bdc3d58f4 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -281,8 +281,8 @@ void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
{codeview::RegisterId::AMD64_XMM31, X86::XMM31},
};
- for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
- MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
+ for (const auto &I : RegMap)
+ MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
}
MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index be85c116bb037..618b97a2e8dbd 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -5490,10 +5490,9 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
/// materialize the FP immediate as a load from a constant pool.
bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
- for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
- if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
+ for (const APFloat &FPImm : LegalFPImmediates)
+ if (Imm.bitwiseIsEqual(FPImm))
return true;
- }
return false;
}
@@ -33438,9 +33437,7 @@ bool X86TargetLowering::areJTsAllowed(const Function *Fn) const {
static bool isEFLAGSLiveAfter(MachineBasicBlock::iterator Itr,
MachineBasicBlock *BB) {
// Scan forward through BB for a use/def of EFLAGS.
- for (MachineBasicBlock::iterator miI = std::next(Itr), miE = BB->end();
- miI != miE; ++miI) {
- const MachineInstr& mi = *miI;
+ for (const MachineInstr &mi : llvm::make_range(std::next(Itr), BB->end())) {
if (mi.readsRegister(X86::EFLAGS))
return true;
// If we found a def, we can stop searching.
diff --git a/llvm/lib/Target/X86/X86PadShortFunction.cpp b/llvm/lib/Target/X86/X86PadShortFunction.cpp
index 47ae517ae76d7..e92b1b002bb01 100644
--- a/llvm/lib/Target/X86/X86PadShortFunction.cpp
+++ b/llvm/lib/Target/X86/X86PadShortFunction.cpp
@@ -129,10 +129,9 @@ bool PadShortFunc::runOnMachineFunction(MachineFunction &MF) {
bool MadeChange = false;
// Pad the identified basic blocks with NOOPs
- for (DenseMap<MachineBasicBlock*, unsigned int>::iterator I = ReturnBBs.begin();
- I != ReturnBBs.end(); ++I) {
- MachineBasicBlock *MBB = I->first;
- unsigned Cycles = I->second;
+ for (const auto &ReturnBB : ReturnBBs) {
+ MachineBasicBlock *MBB = ReturnBB.first;
+ unsigned Cycles = ReturnBB.second;
// Function::hasOptSize is already checked above.
bool OptForSize = llvm::shouldOptimizeForSize(MBB, PSI, MBFI);
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