[llvm] 68b70d1 - [GlobalISel] Fold or of shifts with constant amount to funnel shift.
Abinav Puthan Purayil via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 23 21:21:52 PST 2022
Author: Abinav Puthan Purayil
Date: 2022-01-24T10:43:32+05:30
New Revision: 68b70d17d8dea3fe9fa8e8f8bffd37bfe8125a65
URL: https://github.com/llvm/llvm-project/commit/68b70d17d8dea3fe9fa8e8f8bffd37bfe8125a65
DIFF: https://github.com/llvm/llvm-project/commit/68b70d17d8dea3fe9fa8e8f8bffd37bfe8125a65.diff
LOG: [GlobalISel] Fold or of shifts with constant amount to funnel shift.
This change folds (or (shl x, C0), (lshr y, C1)) to funnel shift iff C0
and C1 are constants where C0 + C1 is the bit-width of the shift
instructions.
Differential Revision: https://reviews.llvm.org/D116529
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/test/CodeGen/AArch64/arm64-rev.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index ed1aa9d80840c..4b5a19155c672 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -3878,39 +3878,48 @@ bool CombinerHelper::matchOrShiftToFunnelShift(MachineInstr &MI,
LLT Ty = MRI.getType(Dst);
unsigned BitWidth = Ty.getScalarSizeInBits();
- Register ShlSrc, ShlAmt, LShrSrc, LShrAmt;
+ Register ShlSrc, ShlAmt, LShrSrc, LShrAmt, Amt;
unsigned FshOpc = 0;
- // Match (or (shl x, amt), (lshr y, sub(bw, amt))).
- if (mi_match(
- Dst, MRI,
- // m_GOr() handles the commuted version as well.
- m_GOr(m_GShl(m_Reg(ShlSrc), m_Reg(ShlAmt)),
- m_GLShr(m_Reg(LShrSrc), m_GSub(m_SpecificICstOrSplat(BitWidth),
- m_Reg(LShrAmt)))))) {
+ // Match (or (shl ...), (lshr ...)).
+ if (!mi_match(Dst, MRI,
+ // m_GOr() handles the commuted version as well.
+ m_GOr(m_GShl(m_Reg(ShlSrc), m_Reg(ShlAmt)),
+ m_GLShr(m_Reg(LShrSrc), m_Reg(LShrAmt)))))
+ return false;
+
+ // Given constants C0 and C1 such that C0 + C1 is bit-width:
+ // (or (shl x, C0), (lshr y, C1)) -> (fshl x, y, C0) or (fshr x, y, C1)
+ // TODO: Match constant splat.
+ int64_t CstShlAmt, CstLShrAmt;
+ if (mi_match(ShlAmt, MRI, m_ICst(CstShlAmt)) &&
+ mi_match(LShrAmt, MRI, m_ICst(CstLShrAmt)) &&
+ CstShlAmt + CstLShrAmt == BitWidth) {
+ FshOpc = TargetOpcode::G_FSHR;
+ Amt = LShrAmt;
+
+ } else if (mi_match(LShrAmt, MRI,
+ m_GSub(m_SpecificICstOrSplat(BitWidth), m_Reg(Amt))) &&
+ ShlAmt == Amt) {
+ // (or (shl x, amt), (lshr y, (sub bw, amt))) -> (fshl x, y, amt)
FshOpc = TargetOpcode::G_FSHL;
- // Match (or (shl x, sub(bw, amt)), (lshr y, amt)).
- } else if (mi_match(Dst, MRI,
- m_GOr(m_GLShr(m_Reg(LShrSrc), m_Reg(LShrAmt)),
- m_GShl(m_Reg(ShlSrc),
- m_GSub(m_SpecificICstOrSplat(BitWidth),
- m_Reg(ShlAmt)))))) {
+ } else if (mi_match(ShlAmt, MRI,
+ m_GSub(m_SpecificICstOrSplat(BitWidth), m_Reg(Amt))) &&
+ LShrAmt == Amt) {
+ // (or (shl x, (sub bw, amt)), (lshr y, amt)) -> (fshr x, y, amt)
FshOpc = TargetOpcode::G_FSHR;
} else {
return false;
}
- if (ShlAmt != LShrAmt)
- return false;
-
- LLT AmtTy = MRI.getType(ShlAmt);
+ LLT AmtTy = MRI.getType(Amt);
if (!isLegalOrBeforeLegalizer({FshOpc, {Ty, AmtTy}}))
return false;
MatchInfo = [=](MachineIRBuilder &B) {
- B.buildInstr(FshOpc, {Dst}, {ShlSrc, LShrSrc, ShlAmt});
+ B.buildInstr(FshOpc, {Dst}, {ShlSrc, LShrSrc, Amt});
};
return true;
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll
index df481b8e39f45..aa223eefbbfaf 100644
--- a/llvm/test/CodeGen/AArch64/arm64-rev.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll
@@ -216,8 +216,7 @@ define i64 @test_rev16_x(i64 %a) nounwind {
; GISEL-LABEL: test_rev16_x:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: rev x8, x0
-; GISEL-NEXT: lsl x9, x8, #48
-; GISEL-NEXT: orr x0, x9, x8, lsr #16
+; GISEL-NEXT: ror x0, x8, #16
; GISEL-NEXT: ret
entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
@@ -235,9 +234,7 @@ define i64 @test_rev32_x(i64 %a) nounwind {
;
; GISEL-LABEL: test_rev32_x:
; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: rev x8, x0
-; GISEL-NEXT: lsl x9, x8, #32
-; GISEL-NEXT: orr x0, x9, x8, lsr #32
+; GISEL-NEXT: rev32 x0, x0
; GISEL-NEXT: ret
entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
index 0e2816cbc9393..ad93f1bf4d39e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
@@ -107,13 +107,66 @@ body: |
...
---
-name: fshl_i32_bad_const
+name: fsh_i32_const
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; CHECK-LABEL: name: fsh_i32_const
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
+ ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: %or:_(s32) = G_FSHR %a, %b, %amt1(s32)
+ ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
+ %a:_(s32) = COPY $vgpr0
+ %b:_(s32) = COPY $vgpr1
+ %amt0:_(s32) = G_CONSTANT i32 20
+ %amt1:_(s32) = G_CONSTANT i32 12
+ %shl:_(s32) = G_SHL %a, %amt0
+ %lshr:_(s32) = G_LSHR %b, %amt1
+ %or:_(s32) = G_OR %shl, %lshr
+ $vgpr2 = COPY %or
+...
+
+---
+name: fsh_i32_bad_const
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; CHECK-LABEL: name: fsh_i32_bad_const
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
+ ; CHECK-NEXT: %amt0:_(s32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt0(s32)
+ ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %b, %amt1(s32)
+ ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
+ ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
+ %a:_(s32) = COPY $vgpr0
+ %b:_(s32) = COPY $vgpr1
+ %amt0:_(s32) = G_CONSTANT i32 20
+ %amt1:_(s32) = G_CONSTANT i32 11
+ %shl:_(s32) = G_SHL %a, %amt0
+ %lshr:_(s32) = G_LSHR %b, %amt1
+ %or:_(s32) = G_OR %shl, %lshr
+ $vgpr2 = COPY %or
+...
+
+---
+name: fshl_i32_bad_bw
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
- ; CHECK-LABEL: name: fshl_i32_bad_const
+ ; CHECK-LABEL: name: fshl_i32_bad_bw
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
index 60791842443d8..2649ee4bdf72a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
@@ -99,13 +99,63 @@ body: |
...
---
-name: rotl_i32_bad_const
+name: rot_i32_const
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: rot_i32_const
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: %or:_(s32) = G_ROTR %a, %amt1(s32)
+ ; CHECK-NEXT: $vgpr1 = COPY %or(s32)
+ %a:_(s32) = COPY $vgpr0
+ %amt0:_(s32) = G_CONSTANT i32 20
+ %amt1:_(s32) = G_CONSTANT i32 12
+ %shl:_(s32) = G_SHL %a, %amt0
+ %lshr:_(s32) = G_LSHR %a, %amt1
+ %or:_(s32) = G_OR %shl, %lshr
+ $vgpr1 = COPY %or
+...
+
+---
+name: rot_i32_bad_const
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: rot_i32_bad_const
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: %amt0:_(s32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt0(s32)
+ ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %amt1(s32)
+ ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
+ ; CHECK-NEXT: $vgpr1 = COPY %or(s32)
+ %a:_(s32) = COPY $vgpr0
+ %amt0:_(s32) = G_CONSTANT i32 20
+ %amt1:_(s32) = G_CONSTANT i32 11
+ %shl:_(s32) = G_SHL %a, %amt0
+ %lshr:_(s32) = G_LSHR %a, %amt1
+ %or:_(s32) = G_OR %shl, %lshr
+ $vgpr1 = COPY %or
+...
+
+
+---
+name: rotl_i32_bad_bw
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
- ; CHECK-LABEL: name: rotl_i32_bad_const
+ ; CHECK-LABEL: name: rotl_i32_bad_bw
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index 0236ebc947267..15755f4455cb5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -52,11 +52,10 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 %node_ptr, float %
; GCN-NEXT: s_mov_b32 s4, 0xffff
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v5
; GCN-NEXT: v_and_b32_e32 v10, s4, v7
-; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_and_b32_e32 v8, s4, v8
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GCN-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GCN-NEXT: v_alignbit_b32 v7, v8, v7, 16
; GCN-NEXT: v_and_or_b32 v5, v5, s4, v9
; GCN-NEXT: v_and_or_b32 v6, v6, s4, v10
; GCN-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
@@ -105,11 +104,10 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 %node_ptr, float
; GCN-NEXT: s_mov_b32 s4, 0xffff
; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v6
; GCN-NEXT: v_and_b32_e32 v11, s4, v8
-; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; GCN-NEXT: v_and_b32_e32 v9, s4, v9
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GCN-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GCN-NEXT: v_alignbit_b32 v8, v9, v8, 16
; GCN-NEXT: v_and_or_b32 v6, v6, s4, v10
; GCN-NEXT: v_and_or_b32 v7, v7, s4, v11
; GCN-NEXT: image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3] a16
@@ -210,16 +208,15 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v5
; GFX1030-NEXT: v_and_b32_e32 v1, s0, v7
; GFX1030-NEXT: v_mov_b32_e32 v15, v2
+; GFX1030-NEXT: v_and_b32_e32 v2, s0, v8
; GFX1030-NEXT: v_mov_b32_e32 v16, v3
-; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 16, v7
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1030-NEXT: v_and_b32_e32 v3, s0, v8
; GFX1030-NEXT: v_mov_b32_e32 v17, v4
+; GFX1030-NEXT: v_alignbit_b32 v20, v2, v7, 16
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: v_and_or_b32 v18, v5, s0, v0
; GFX1030-NEXT: v_and_or_b32 v19, v6, s0, v1
-; GFX1030-NEXT: v_lshl_or_b32 v20, v3, 16, v2
; GFX1030-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v9
; GFX1030-NEXT: v_readfirstlane_b32 s5, v10
@@ -252,12 +249,11 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
; GFX1013-NEXT: s_mov_b32 s0, 0xffff
; GFX1013-NEXT: v_lshrrev_b32_e32 v13, 16, v5
; GFX1013-NEXT: v_and_b32_e32 v14, s0, v7
-; GFX1013-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX1013-NEXT: v_and_b32_e32 v8, s0, v8
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX1013-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX1013-NEXT: v_alignbit_b32 v7, v8, v7, 16
; GFX1013-NEXT: v_and_or_b32 v5, v5, s0, v13
; GFX1013-NEXT: v_and_or_b32 v6, v6, s0, v14
; GFX1013-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
@@ -381,16 +377,15 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node
; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v6
; GFX1030-NEXT: v_and_b32_e32 v1, s0, v8
; GFX1030-NEXT: v_mov_b32_e32 v16, v2
+; GFX1030-NEXT: v_and_b32_e32 v2, s0, v9
; GFX1030-NEXT: v_mov_b32_e32 v17, v3
-; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 16, v8
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1030-NEXT: v_and_b32_e32 v3, s0, v9
; GFX1030-NEXT: v_mov_b32_e32 v18, v4
; GFX1030-NEXT: v_mov_b32_e32 v19, v5
+; GFX1030-NEXT: v_alignbit_b32 v22, v2, v8, 16
; GFX1030-NEXT: v_and_or_b32 v20, v6, s0, v0
; GFX1030-NEXT: v_and_or_b32 v21, v7, s0, v1
-; GFX1030-NEXT: v_lshl_or_b32 v22, v3, 16, v2
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v10
@@ -427,13 +422,12 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node
; GFX1013-NEXT: v_mov_b32_e32 v17, v11
; GFX1013-NEXT: v_lshrrev_b32_e32 v10, 16, v6
; GFX1013-NEXT: v_and_b32_e32 v11, s0, v8
-; GFX1013-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; GFX1013-NEXT: v_and_b32_e32 v9, s0, v9
; GFX1013-NEXT: v_mov_b32_e32 v18, v12
+; GFX1013-NEXT: v_mov_b32_e32 v19, v13
; GFX1013-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX1013-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX1013-NEXT: v_mov_b32_e32 v19, v13
-; GFX1013-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX1013-NEXT: v_alignbit_b32 v8, v9, v8, 16
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: v_and_or_b32 v6, v6, s0, v10
; GFX1013-NEXT: v_and_or_b32 v7, v7, s0, v11
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
index 503b45d49991c..c248c4236e067 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
@@ -383,14 +383,12 @@ define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_min_u32_e32 v4, v5, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 24
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v3
@@ -534,18 +532,18 @@ define amdgpu_ps i32 @s_uaddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX6-NEXT: s_lshl_b32 s3, s4, 24
; GFX6-NEXT: s_lshl_b32 s4, s7, 24
; GFX6-NEXT: s_not_b32 s5, s3
-; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_min_u32 s4, s5, s4
-; GFX6-NEXT: s_lshr_b32 s0, s0, 24
+; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_lshr_b32 s2, s2, 24
; GFX6-NEXT: s_add_i32 s3, s3, s4
-; GFX6-NEXT: s_lshl_b32 s1, s1, 8
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_lshr_b32 s3, s3, 24
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s2, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s3, 24
-; GFX6-NEXT: s_or_b32 s0, s0, s1
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 24
+; GFX6-NEXT: s_lshl_b32 s0, s2, 16
+; GFX6-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX6-NEXT: s_lshl_b32 s0, s3, 24
+; GFX6-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_uaddsat_v4i8:
@@ -1814,9 +1812,9 @@ define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
; GFX6-NEXT: s_min_u32 s2, s3, s2
; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 16
-; GFX6-NEXT: s_lshr_b32 s0, s0, 16
-; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 16
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_uaddsat_v2i16:
@@ -1864,9 +1862,7 @@ define amdgpu_ps float @uaddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX6-NEXT: v_min_u32_e32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: uaddsat_v2i16_sv:
@@ -1908,9 +1904,7 @@ define amdgpu_ps float @uaddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-NEXT: v_min_u32_e32 v2, s0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: uaddsat_v2i16_vs:
@@ -1972,15 +1966,11 @@ define <2 x float> @v_uaddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v3
; GFX6-NEXT: v_min_u32_e32 v4, v5, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, v3, v2, 16
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_uaddsat_v4i16:
@@ -2038,15 +2028,15 @@ define amdgpu_ps <2 x i32> @s_uaddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
; GFX6-NEXT: s_lshl_b32 s4, s7, 16
; GFX6-NEXT: s_not_b32 s5, s3
; GFX6-NEXT: s_min_u32 s4, s5, s4
-; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_add_i32 s3, s3, s4
-; GFX6-NEXT: s_lshr_b32 s0, s0, 16
+; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
-; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_lshr_b32 s2, s2, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s3, 16
-; GFX6-NEXT: s_or_b32 s1, s2, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_uaddsat_v4i16:
@@ -2137,20 +2127,14 @@ define <3 x float> @v_uaddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v11
; GFX6-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_u32_e32 v6, v7, v6
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX6-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, v3, v2, 16
+; GFX6-NEXT: v_alignbit_b32 v2, v5, v4, 16
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_uaddsat_v6i16:
@@ -2224,20 +2208,20 @@ define amdgpu_ps <3 x i32> @s_uaddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
; GFX6-NEXT: s_add_i32 s4, s4, s6
; GFX6-NEXT: s_lshl_b32 s6, s11, 16
; GFX6-NEXT: s_not_b32 s7, s5
-; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_min_u32 s6, s7, s6
-; GFX6-NEXT: s_lshr_b32 s0, s0, 16
-; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_add_i32 s5, s5, s6
-; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_lshr_b32 s2, s2, 16
+; GFX6-NEXT: s_lshr_b32 s1, s1, 16
+; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_lshr_b32 s5, s5, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s3, 16
-; GFX6-NEXT: s_lshr_b32 s4, s4, 16
-; GFX6-NEXT: s_or_b32 s1, s2, s1
-; GFX6-NEXT: s_lshl_b32 s2, s5, 16
-; GFX6-NEXT: s_or_b32 s2, s4, s2
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT: v_alignbit_b32 v2, s5, v2, 16
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s2, v2
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_uaddsat_v6i16:
@@ -2341,24 +2325,16 @@ define <4 x float> @v_uaddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v15
; GFX6-NEXT: v_xor_b32_e32 v9, -1, v7
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_u32_e32 v8, v9, v8
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v8
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX6-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, v3, v2, 16
+; GFX6-NEXT: v_alignbit_b32 v2, v5, v4, 16
+; GFX6-NEXT: v_alignbit_b32 v3, v7, v6, 16
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_uaddsat_v8i16:
@@ -2448,24 +2424,24 @@ define amdgpu_ps <4 x i32> @s_uaddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
; GFX6-NEXT: s_add_i32 s6, s6, s8
; GFX6-NEXT: s_lshl_b32 s8, s15, 16
; GFX6-NEXT: s_not_b32 s9, s7
-; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_min_u32 s8, s9, s8
-; GFX6-NEXT: s_lshr_b32 s0, s0, 16
-; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_add_i32 s7, s7, s8
-; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_lshr_b32 s2, s2, 16
+; GFX6-NEXT: s_lshr_b32 s1, s1, 16
+; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_lshr_b32 s5, s5, 16
; GFX6-NEXT: s_lshr_b32 s7, s7, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s3, 16
-; GFX6-NEXT: s_lshr_b32 s4, s4, 16
-; GFX6-NEXT: s_lshr_b32 s6, s6, 16
-; GFX6-NEXT: s_or_b32 s1, s2, s1
-; GFX6-NEXT: s_lshl_b32 s2, s5, 16
-; GFX6-NEXT: s_lshl_b32 s3, s7, 16
-; GFX6-NEXT: s_or_b32 s2, s4, s2
-; GFX6-NEXT: s_or_b32 s3, s6, s3
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: v_mov_b32_e32 v3, s6
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT: v_alignbit_b32 v2, s5, v2, 16
+; GFX6-NEXT: v_alignbit_b32 v3, s7, v3, 16
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s2, v2
+; GFX6-NEXT: v_readfirstlane_b32 s3, v3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_uaddsat_v8i16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
index a4da5822dac57..9676db3eba17e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
@@ -371,14 +371,12 @@ define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_min_u32_e32 v4, v3, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 24
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v3
@@ -518,18 +516,18 @@ define amdgpu_ps i32 @s_usubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24
; GFX6-NEXT: s_lshl_b32 s4, s7, 24
-; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_min_u32 s4, s3, s4
-; GFX6-NEXT: s_lshr_b32 s0, s0, 24
+; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_lshr_b32 s2, s2, 24
; GFX6-NEXT: s_sub_i32 s3, s3, s4
-; GFX6-NEXT: s_lshl_b32 s1, s1, 8
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_lshr_b32 s3, s3, 24
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s2, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s3, 24
-; GFX6-NEXT: s_or_b32 s0, s0, s1
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 24
+; GFX6-NEXT: s_lshl_b32 s0, s2, 16
+; GFX6-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX6-NEXT: s_lshl_b32 s0, s3, 24
+; GFX6-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_usubsat_v4i8:
@@ -1724,9 +1722,9 @@ define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
; GFX6-NEXT: s_min_u32 s2, s1, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 16
-; GFX6-NEXT: s_lshr_b32 s0, s0, 16
-; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 16
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_usubsat_v2i16:
@@ -1772,9 +1770,7 @@ define amdgpu_ps float @usubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX6-NEXT: v_min_u32_e32 v1, s0, v1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: usubsat_v2i16_sv:
@@ -1814,9 +1810,7 @@ define amdgpu_ps float @usubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-NEXT: v_min_u32_e32 v2, s0, v1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: usubsat_v2i16_vs:
@@ -1874,15 +1868,11 @@ define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7
; GFX6-NEXT: v_min_u32_e32 v4, v3, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, v3, v2, 16
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_usubsat_v4i16:
@@ -1936,15 +1926,15 @@ define amdgpu_ps <2 x i32> @s_usubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s7, 16
; GFX6-NEXT: s_min_u32 s4, s3, s4
-; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_sub_i32 s3, s3, s4
-; GFX6-NEXT: s_lshr_b32 s0, s0, 16
+; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
-; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_lshr_b32 s2, s2, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s3, 16
-; GFX6-NEXT: s_or_b32 s1, s2, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_usubsat_v4i16:
@@ -2029,20 +2019,14 @@ define <3 x float> @v_usubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v11
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_u32_e32 v6, v5, v6
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v6
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX6-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, v3, v2, 16
+; GFX6-NEXT: v_alignbit_b32 v2, v5, v4, 16
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_usubsat_v6i16:
@@ -2110,20 +2094,20 @@ define amdgpu_ps <3 x i32> @s_usubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
; GFX6-NEXT: s_sub_i32 s4, s4, s6
; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s6, s11, 16
-; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_min_u32 s6, s5, s6
-; GFX6-NEXT: s_lshr_b32 s0, s0, 16
-; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_sub_i32 s5, s5, s6
-; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_lshr_b32 s2, s2, 16
+; GFX6-NEXT: s_lshr_b32 s1, s1, 16
+; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_lshr_b32 s5, s5, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s3, 16
-; GFX6-NEXT: s_lshr_b32 s4, s4, 16
-; GFX6-NEXT: s_or_b32 s1, s2, s1
-; GFX6-NEXT: s_lshl_b32 s2, s5, 16
-; GFX6-NEXT: s_or_b32 s2, s4, s2
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT: v_alignbit_b32 v2, s5, v2, 16
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s2, v2
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_usubsat_v6i16:
@@ -2219,24 +2203,16 @@ define <4 x float> @v_usubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v15
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_u32_e32 v8, v7, v8
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v8
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX6-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, v3, v2, 16
+; GFX6-NEXT: v_alignbit_b32 v2, v5, v4, 16
+; GFX6-NEXT: v_alignbit_b32 v3, v7, v6, 16
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_usubsat_v8i16:
@@ -2318,24 +2294,24 @@ define amdgpu_ps <4 x i32> @s_usubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
; GFX6-NEXT: s_sub_i32 s6, s6, s8
; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_lshl_b32 s8, s15, 16
-; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_min_u32 s8, s7, s8
-; GFX6-NEXT: s_lshr_b32 s0, s0, 16
-; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_sub_i32 s7, s7, s8
-; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_lshr_b32 s2, s2, 16
+; GFX6-NEXT: s_lshr_b32 s1, s1, 16
+; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_lshr_b32 s5, s5, 16
; GFX6-NEXT: s_lshr_b32 s7, s7, 16
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: s_lshl_b32 s1, s3, 16
-; GFX6-NEXT: s_lshr_b32 s4, s4, 16
-; GFX6-NEXT: s_lshr_b32 s6, s6, 16
-; GFX6-NEXT: s_or_b32 s1, s2, s1
-; GFX6-NEXT: s_lshl_b32 s2, s5, 16
-; GFX6-NEXT: s_lshl_b32 s3, s7, 16
-; GFX6-NEXT: s_or_b32 s2, s4, s2
-; GFX6-NEXT: s_or_b32 s3, s6, s3
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: v_mov_b32_e32 v3, s6
+; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 16
+; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT: v_alignbit_b32 v2, s5, v2, 16
+; GFX6-NEXT: v_alignbit_b32 v3, s7, v3, 16
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s2, v2
+; GFX6-NEXT: v_readfirstlane_b32 s3, v3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_usubsat_v8i16:
More information about the llvm-commits
mailing list