[llvm] 3575700 - [RISCV] Add tests that do a bitreverse before or after a bswap. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 23 13:46:26 PST 2022
Author: Craig Topper
Date: 2022-01-23T13:44:31-08:00
New Revision: 3575700b286f8c3150abb3de7968a9f36dd1cceb
URL: https://github.com/llvm/llvm-project/commit/3575700b286f8c3150abb3de7968a9f36dd1cceb
DIFF: https://github.com/llvm/llvm-project/commit/3575700b286f8c3150abb3de7968a9f36dd1cceb.diff
LOG: [RISCV] Add tests that do a bitreverse before or after a bswap. NFC
We don't optimize this as well as we could. Bitreverse is always
expanded to bswap and a shift/and/or sequence to swap bits within a
byte. The newly created bswap will either becomes a shift/and/or
sequence or rev8 instruction. We don't always realize the bswap is
redundant with another bswap before or after the bitreverse.
Found while thinking about the brev8 instruction from the
Cryptography extension. It's equivalent to bswap(bitreverse(x)) or
bitreverse(bswap(x)).
Added:
Modified:
llvm/test/CodeGen/RISCV/bswap-bitreverse-ctlz-cttz-ctpop.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/bswap-bitreverse-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-bitreverse-ctlz-cttz-ctpop.ll
index 8a0c0db7aaa3..435ea9c0d80d 100644
--- a/llvm/test/CodeGen/RISCV/bswap-bitreverse-ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-bitreverse-ctlz-cttz-ctpop.ll
@@ -691,11 +691,1021 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind {
ret i64 %tmp
}
+define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind {
+; RV32I-LABEL: test_bswap_bitreverse_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a0, 8
+; RV32I-NEXT: slli a2, a0, 16
+; RV32I-NEXT: srli a2, a2, 24
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: slli a1, a1, 8
+; RV32I-NEXT: andi a0, a0, 255
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 4
+; RV32I-NEXT: lui a2, 1
+; RV32I-NEXT: addi a2, a2, -241
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 2
+; RV32I-NEXT: lui a2, 3
+; RV32I-NEXT: addi a2, a2, 819
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 1
+; RV32I-NEXT: lui a2, 5
+; RV32I-NEXT: addi a2, a2, 1365
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_bswap_bitreverse_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 8
+; RV64I-NEXT: slli a2, a0, 48
+; RV64I-NEXT: srli a2, a2, 56
+; RV64I-NEXT: or a1, a1, a2
+; RV64I-NEXT: slli a1, a1, 8
+; RV64I-NEXT: andi a0, a0, 255
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: lui a2, 1
+; RV64I-NEXT: addiw a2, a2, -241
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 4
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 2
+; RV64I-NEXT: lui a2, 3
+; RV64I-NEXT: addiw a2, a2, 819
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 1
+; RV64I-NEXT: lui a2, 5
+; RV64I-NEXT: addiw a2, a2, 1365
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ret
+;
+; RV32ZBB-LABEL: test_bswap_bitreverse_i16:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: rev8 a0, a0
+; RV32ZBB-NEXT: srli a0, a0, 16
+; RV32ZBB-NEXT: rev8 a0, a0
+; RV32ZBB-NEXT: srli a1, a0, 12
+; RV32ZBB-NEXT: lui a2, 15
+; RV32ZBB-NEXT: addi a2, a2, 240
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: srli a0, a0, 20
+; RV32ZBB-NEXT: andi a0, a0, -241
+; RV32ZBB-NEXT: or a0, a0, a1
+; RV32ZBB-NEXT: srli a1, a0, 2
+; RV32ZBB-NEXT: lui a2, 3
+; RV32ZBB-NEXT: addi a2, a2, 819
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 2
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: srli a1, a0, 1
+; RV32ZBB-NEXT: lui a2, 5
+; RV32ZBB-NEXT: addi a2, a2, 1365
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 1
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: ret
+;
+; RV64ZBB-LABEL: test_bswap_bitreverse_i16:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srli a0, a0, 48
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srli a1, a0, 44
+; RV64ZBB-NEXT: lui a2, 15
+; RV64ZBB-NEXT: addiw a2, a2, 240
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: srli a0, a0, 52
+; RV64ZBB-NEXT: andi a0, a0, -241
+; RV64ZBB-NEXT: or a0, a0, a1
+; RV64ZBB-NEXT: srli a1, a0, 2
+; RV64ZBB-NEXT: lui a2, 3
+; RV64ZBB-NEXT: addiw a2, a2, 819
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: slli a0, a0, 2
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: srli a1, a0, 1
+; RV64ZBB-NEXT: lui a2, 5
+; RV64ZBB-NEXT: addiw a2, a2, 1365
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: slli a0, a0, 1
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: ret
+ %tmp = call i16 @llvm.bswap.i16(i16 %a)
+ %tmp2 = call i16 @llvm.bitreverse.i16(i16 %tmp)
+ ret i16 %tmp2
+}
+
+define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind {
+; RV32I-LABEL: test_bswap_bitreverse_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a1, a0, 8
+; RV32I-NEXT: lui a2, 16
+; RV32I-NEXT: addi a2, a2, -256
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srli a3, a0, 24
+; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: slli a3, a0, 8
+; RV32I-NEXT: lui a4, 4080
+; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a0, a0, a3
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: srli a1, a0, 8
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srli a2, a0, 24
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: slli a2, a0, 8
+; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a0, a0, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: srli a1, a0, 4
+; RV32I-NEXT: lui a2, 61681
+; RV32I-NEXT: addi a2, a2, -241
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 2
+; RV32I-NEXT: lui a2, 209715
+; RV32I-NEXT: addi a2, a2, 819
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 1
+; RV32I-NEXT: lui a2, 349525
+; RV32I-NEXT: addi a2, a2, 1365
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_bswap_bitreverse_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srliw a1, a0, 8
+; RV64I-NEXT: lui a2, 16
+; RV64I-NEXT: addiw a2, a2, -256
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srliw a3, a0, 24
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: slli a3, a0, 8
+; RV64I-NEXT: lui a4, 4080
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: slliw a0, a0, 24
+; RV64I-NEXT: or a0, a0, a3
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: srliw a1, a0, 8
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srliw a2, a0, 24
+; RV64I-NEXT: or a1, a1, a2
+; RV64I-NEXT: slli a2, a0, 8
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: slliw a0, a0, 24
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: lui a2, 61681
+; RV64I-NEXT: addiw a2, a2, -241
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slliw a0, a0, 4
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 2
+; RV64I-NEXT: lui a2, 209715
+; RV64I-NEXT: addiw a2, a2, 819
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slliw a0, a0, 2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 1
+; RV64I-NEXT: lui a2, 349525
+; RV64I-NEXT: addiw a2, a2, 1365
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slliw a0, a0, 1
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ret
+;
+; RV32ZBB-LABEL: test_bswap_bitreverse_i32:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: srli a1, a0, 4
+; RV32ZBB-NEXT: lui a2, 61681
+; RV32ZBB-NEXT: addi a2, a2, -241
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 4
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: srli a1, a0, 2
+; RV32ZBB-NEXT: lui a2, 209715
+; RV32ZBB-NEXT: addi a2, a2, 819
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 2
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: srli a1, a0, 1
+; RV32ZBB-NEXT: lui a2, 349525
+; RV32ZBB-NEXT: addi a2, a2, 1365
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 1
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: ret
+;
+; RV64ZBB-LABEL: test_bswap_bitreverse_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srli a0, a0, 32
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srli a1, a0, 36
+; RV64ZBB-NEXT: lui a2, 61681
+; RV64ZBB-NEXT: addiw a2, a2, -241
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: srli a0, a0, 28
+; RV64ZBB-NEXT: lui a2, 986895
+; RV64ZBB-NEXT: addiw a2, a2, 240
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: sext.w a0, a0
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: srli a1, a0, 2
+; RV64ZBB-NEXT: lui a2, 209715
+; RV64ZBB-NEXT: addiw a2, a2, 819
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: slliw a0, a0, 2
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: srli a1, a0, 1
+; RV64ZBB-NEXT: lui a2, 349525
+; RV64ZBB-NEXT: addiw a2, a2, 1365
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: slliw a0, a0, 1
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: ret
+ %tmp = call i32 @llvm.bswap.i32(i32 %a)
+ %tmp2 = call i32 @llvm.bitreverse.i32(i32 %tmp)
+ ret i32 %tmp2
+}
+
+define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind {
+; RV32I-LABEL: test_bswap_bitreverse_i64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a2, a1, 8
+; RV32I-NEXT: lui a3, 16
+; RV32I-NEXT: addi a3, a3, -256
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: srli a4, a1, 24
+; RV32I-NEXT: or a2, a2, a4
+; RV32I-NEXT: slli a4, a1, 8
+; RV32I-NEXT: lui a5, 4080
+; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: slli a1, a1, 24
+; RV32I-NEXT: or a1, a1, a4
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: srli a2, a0, 8
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: srli a4, a0, 24
+; RV32I-NEXT: or a2, a2, a4
+; RV32I-NEXT: slli a4, a0, 8
+; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a0, a0, a4
+; RV32I-NEXT: or a0, a0, a2
+; RV32I-NEXT: srli a2, a0, 8
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: srli a4, a0, 24
+; RV32I-NEXT: or a2, a2, a4
+; RV32I-NEXT: slli a4, a0, 8
+; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a0, a0, a4
+; RV32I-NEXT: or a0, a0, a2
+; RV32I-NEXT: srli a2, a0, 4
+; RV32I-NEXT: lui a4, 61681
+; RV32I-NEXT: addi a4, a4, -241
+; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: and a0, a0, a4
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: srli a2, a0, 2
+; RV32I-NEXT: lui a6, 209715
+; RV32I-NEXT: addi a6, a6, 819
+; RV32I-NEXT: and a2, a2, a6
+; RV32I-NEXT: and a0, a0, a6
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: srli a2, a0, 1
+; RV32I-NEXT: lui a7, 349525
+; RV32I-NEXT: addi a7, a7, 1365
+; RV32I-NEXT: and a2, a2, a7
+; RV32I-NEXT: and a0, a0, a7
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: srli a2, a1, 8
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: srli a3, a1, 24
+; RV32I-NEXT: or a2, a2, a3
+; RV32I-NEXT: slli a3, a1, 8
+; RV32I-NEXT: and a3, a3, a5
+; RV32I-NEXT: slli a1, a1, 24
+; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: srli a2, a1, 4
+; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: slli a1, a1, 4
+; RV32I-NEXT: or a1, a2, a1
+; RV32I-NEXT: srli a2, a1, 2
+; RV32I-NEXT: and a2, a2, a6
+; RV32I-NEXT: and a1, a1, a6
+; RV32I-NEXT: slli a1, a1, 2
+; RV32I-NEXT: or a1, a2, a1
+; RV32I-NEXT: srli a2, a1, 1
+; RV32I-NEXT: and a2, a2, a7
+; RV32I-NEXT: and a1, a1, a7
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: or a1, a2, a1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_bswap_bitreverse_i64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srli a1, a0, 24
+; RV64I-NEXT: lui a2, 4080
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srli a3, a0, 8
+; RV64I-NEXT: li a4, 255
+; RV64I-NEXT: slli a5, a4, 24
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: or a1, a3, a1
+; RV64I-NEXT: srli a3, a0, 40
+; RV64I-NEXT: lui a6, 16
+; RV64I-NEXT: addiw a6, a6, -256
+; RV64I-NEXT: and a3, a3, a6
+; RV64I-NEXT: srli a7, a0, 56
+; RV64I-NEXT: or a3, a3, a7
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: slli a3, a0, 24
+; RV64I-NEXT: slli a7, a4, 40
+; RV64I-NEXT: and a3, a3, a7
+; RV64I-NEXT: srliw t0, a0, 24
+; RV64I-NEXT: slli t0, t0, 32
+; RV64I-NEXT: or a3, a3, t0
+; RV64I-NEXT: slli t0, a0, 40
+; RV64I-NEXT: slli a4, a4, 48
+; RV64I-NEXT: and t0, t0, a4
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: or a0, a0, t0
+; RV64I-NEXT: or a0, a0, a3
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: srli a1, a0, 40
+; RV64I-NEXT: and a1, a1, a6
+; RV64I-NEXT: srli a3, a0, 56
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: srli a3, a0, 24
+; RV64I-NEXT: and a2, a3, a2
+; RV64I-NEXT: srli a3, a0, 8
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: or a2, a3, a2
+; RV64I-NEXT: or a1, a2, a1
+; RV64I-NEXT: slli a2, a0, 24
+; RV64I-NEXT: and a2, a2, a7
+; RV64I-NEXT: srliw a3, a0, 24
+; RV64I-NEXT: slli a3, a3, 32
+; RV64I-NEXT: or a2, a2, a3
+; RV64I-NEXT: slli a3, a0, 40
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: or a0, a0, a3
+; RV64I-NEXT: lui a3, %hi(.LCPI9_0)
+; RV64I-NEXT: ld a3, %lo(.LCPI9_0)(a3)
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: lui a2, %hi(.LCPI9_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI9_1)(a2)
+; RV64I-NEXT: slli a0, a0, 4
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 2
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: lui a2, %hi(.LCPI9_2)
+; RV64I-NEXT: ld a2, %lo(.LCPI9_2)(a2)
+; RV64I-NEXT: slli a0, a0, 2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 1
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ret
+;
+; RV32ZBB-LABEL: test_bswap_bitreverse_i64:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: srli a2, a0, 4
+; RV32ZBB-NEXT: lui a3, 61681
+; RV32ZBB-NEXT: addi a3, a3, -241
+; RV32ZBB-NEXT: and a2, a2, a3
+; RV32ZBB-NEXT: and a0, a0, a3
+; RV32ZBB-NEXT: slli a0, a0, 4
+; RV32ZBB-NEXT: or a0, a2, a0
+; RV32ZBB-NEXT: srli a2, a0, 2
+; RV32ZBB-NEXT: lui a4, 209715
+; RV32ZBB-NEXT: addi a4, a4, 819
+; RV32ZBB-NEXT: and a2, a2, a4
+; RV32ZBB-NEXT: and a0, a0, a4
+; RV32ZBB-NEXT: slli a0, a0, 2
+; RV32ZBB-NEXT: or a0, a2, a0
+; RV32ZBB-NEXT: srli a2, a0, 1
+; RV32ZBB-NEXT: lui a5, 349525
+; RV32ZBB-NEXT: addi a5, a5, 1365
+; RV32ZBB-NEXT: and a2, a2, a5
+; RV32ZBB-NEXT: and a0, a0, a5
+; RV32ZBB-NEXT: slli a0, a0, 1
+; RV32ZBB-NEXT: or a0, a2, a0
+; RV32ZBB-NEXT: srli a2, a1, 4
+; RV32ZBB-NEXT: and a2, a2, a3
+; RV32ZBB-NEXT: and a1, a1, a3
+; RV32ZBB-NEXT: slli a1, a1, 4
+; RV32ZBB-NEXT: or a1, a2, a1
+; RV32ZBB-NEXT: srli a2, a1, 2
+; RV32ZBB-NEXT: and a2, a2, a4
+; RV32ZBB-NEXT: and a1, a1, a4
+; RV32ZBB-NEXT: slli a1, a1, 2
+; RV32ZBB-NEXT: or a1, a2, a1
+; RV32ZBB-NEXT: srli a2, a1, 1
+; RV32ZBB-NEXT: and a2, a2, a5
+; RV32ZBB-NEXT: and a1, a1, a5
+; RV32ZBB-NEXT: slli a1, a1, 1
+; RV32ZBB-NEXT: or a1, a2, a1
+; RV32ZBB-NEXT: ret
+;
+; RV64ZBB-LABEL: test_bswap_bitreverse_i64:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: lui a1, %hi(.LCPI9_0)
+; RV64ZBB-NEXT: ld a1, %lo(.LCPI9_0)(a1)
+; RV64ZBB-NEXT: srli a2, a0, 4
+; RV64ZBB-NEXT: and a2, a2, a1
+; RV64ZBB-NEXT: and a0, a0, a1
+; RV64ZBB-NEXT: lui a1, %hi(.LCPI9_1)
+; RV64ZBB-NEXT: ld a1, %lo(.LCPI9_1)(a1)
+; RV64ZBB-NEXT: slli a0, a0, 4
+; RV64ZBB-NEXT: or a0, a2, a0
+; RV64ZBB-NEXT: srli a2, a0, 2
+; RV64ZBB-NEXT: and a2, a2, a1
+; RV64ZBB-NEXT: and a0, a0, a1
+; RV64ZBB-NEXT: lui a1, %hi(.LCPI9_2)
+; RV64ZBB-NEXT: ld a1, %lo(.LCPI9_2)(a1)
+; RV64ZBB-NEXT: slli a0, a0, 2
+; RV64ZBB-NEXT: or a0, a2, a0
+; RV64ZBB-NEXT: srli a2, a0, 1
+; RV64ZBB-NEXT: and a2, a2, a1
+; RV64ZBB-NEXT: and a0, a0, a1
+; RV64ZBB-NEXT: slli a0, a0, 1
+; RV64ZBB-NEXT: or a0, a2, a0
+; RV64ZBB-NEXT: ret
+ %tmp = call i64 @llvm.bswap.i64(i64 %a)
+ %tmp2 = call i64 @llvm.bitreverse.i64(i64 %tmp)
+ ret i64 %tmp2
+}
+
+define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind {
+; RV32I-LABEL: test_bitreverse_bswap_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a0, 8
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srli a0, a0, 24
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 4
+; RV32I-NEXT: lui a2, 1
+; RV32I-NEXT: addi a2, a2, -241
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 2
+; RV32I-NEXT: lui a2, 3
+; RV32I-NEXT: addi a2, a2, 819
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 1
+; RV32I-NEXT: lui a2, 5
+; RV32I-NEXT: addi a2, a2, 1365
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 8
+; RV32I-NEXT: slli a0, a0, 8
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_bitreverse_bswap_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 8
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: lui a2, 1
+; RV64I-NEXT: addiw a2, a2, -241
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 4
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 2
+; RV64I-NEXT: lui a2, 3
+; RV64I-NEXT: addiw a2, a2, 819
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 1
+; RV64I-NEXT: lui a2, 5
+; RV64I-NEXT: addiw a2, a2, 1365
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 8
+; RV64I-NEXT: slli a0, a0, 8
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV32ZBB-LABEL: test_bitreverse_bswap_i16:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: rev8 a0, a0
+; RV32ZBB-NEXT: srli a1, a0, 12
+; RV32ZBB-NEXT: lui a2, 15
+; RV32ZBB-NEXT: addi a2, a2, 240
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: srli a0, a0, 20
+; RV32ZBB-NEXT: andi a0, a0, -241
+; RV32ZBB-NEXT: or a0, a0, a1
+; RV32ZBB-NEXT: srli a1, a0, 2
+; RV32ZBB-NEXT: lui a2, 3
+; RV32ZBB-NEXT: addi a2, a2, 819
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 2
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: srli a1, a0, 1
+; RV32ZBB-NEXT: lui a2, 5
+; RV32ZBB-NEXT: addi a2, a2, 1365
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 1
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: rev8 a0, a0
+; RV32ZBB-NEXT: srli a0, a0, 16
+; RV32ZBB-NEXT: ret
+;
+; RV64ZBB-LABEL: test_bitreverse_bswap_i16:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srli a1, a0, 44
+; RV64ZBB-NEXT: lui a2, 15
+; RV64ZBB-NEXT: addiw a2, a2, 240
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: srli a0, a0, 52
+; RV64ZBB-NEXT: andi a0, a0, -241
+; RV64ZBB-NEXT: or a0, a0, a1
+; RV64ZBB-NEXT: srli a1, a0, 2
+; RV64ZBB-NEXT: lui a2, 3
+; RV64ZBB-NEXT: addiw a2, a2, 819
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: slli a0, a0, 2
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: srli a1, a0, 1
+; RV64ZBB-NEXT: lui a2, 5
+; RV64ZBB-NEXT: addiw a2, a2, 1365
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: slli a0, a0, 1
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srli a0, a0, 48
+; RV64ZBB-NEXT: ret
+ %tmp = call i16 @llvm.bitreverse.i16(i16 %a)
+ %tmp2 = call i16 @llvm.bswap.i16(i16 %tmp)
+ ret i16 %tmp2
+}
+
+define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind {
+; RV32I-LABEL: test_bitreverse_bswap_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a1, a0, 8
+; RV32I-NEXT: lui a2, 16
+; RV32I-NEXT: addi a2, a2, -256
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srli a3, a0, 24
+; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: slli a3, a0, 8
+; RV32I-NEXT: lui a4, 4080
+; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a0, a0, a3
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: srli a1, a0, 4
+; RV32I-NEXT: lui a3, 61681
+; RV32I-NEXT: addi a3, a3, -241
+; RV32I-NEXT: and a1, a1, a3
+; RV32I-NEXT: and a0, a0, a3
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 2
+; RV32I-NEXT: lui a3, 209715
+; RV32I-NEXT: addi a3, a3, 819
+; RV32I-NEXT: and a1, a1, a3
+; RV32I-NEXT: and a0, a0, a3
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 1
+; RV32I-NEXT: lui a3, 349525
+; RV32I-NEXT: addi a3, a3, 1365
+; RV32I-NEXT: and a1, a1, a3
+; RV32I-NEXT: and a0, a0, a3
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: srli a1, a0, 8
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srli a2, a0, 24
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: slli a2, a0, 8
+; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a0, a0, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_bitreverse_bswap_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srliw a1, a0, 8
+; RV64I-NEXT: lui a2, 16
+; RV64I-NEXT: addiw a2, a2, -256
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srliw a3, a0, 24
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: slli a3, a0, 8
+; RV64I-NEXT: lui a4, 4080
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: slliw a0, a0, 24
+; RV64I-NEXT: or a0, a0, a3
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: lui a3, 61681
+; RV64I-NEXT: addiw a3, a3, -241
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: slliw a0, a0, 4
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 2
+; RV64I-NEXT: lui a3, 209715
+; RV64I-NEXT: addiw a3, a3, 819
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: slliw a0, a0, 2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 1
+; RV64I-NEXT: lui a3, 349525
+; RV64I-NEXT: addiw a3, a3, 1365
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: slliw a0, a0, 1
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srliw a1, a0, 8
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srliw a2, a0, 24
+; RV64I-NEXT: or a1, a1, a2
+; RV64I-NEXT: slli a2, a0, 8
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: slliw a0, a0, 24
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV32ZBB-LABEL: test_bitreverse_bswap_i32:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: rev8 a0, a0
+; RV32ZBB-NEXT: srli a1, a0, 4
+; RV32ZBB-NEXT: lui a2, 61681
+; RV32ZBB-NEXT: addi a2, a2, -241
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 4
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: srli a1, a0, 2
+; RV32ZBB-NEXT: lui a2, 209715
+; RV32ZBB-NEXT: addi a2, a2, 819
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 2
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: srli a1, a0, 1
+; RV32ZBB-NEXT: lui a2, 349525
+; RV32ZBB-NEXT: addi a2, a2, 1365
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a0, a0, 1
+; RV32ZBB-NEXT: or a0, a1, a0
+; RV32ZBB-NEXT: rev8 a0, a0
+; RV32ZBB-NEXT: ret
+;
+; RV64ZBB-LABEL: test_bitreverse_bswap_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srli a1, a0, 36
+; RV64ZBB-NEXT: lui a2, 61681
+; RV64ZBB-NEXT: addiw a2, a2, -241
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: srli a0, a0, 28
+; RV64ZBB-NEXT: lui a2, 986895
+; RV64ZBB-NEXT: addiw a2, a2, 240
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: sext.w a0, a0
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: srli a1, a0, 2
+; RV64ZBB-NEXT: lui a2, 209715
+; RV64ZBB-NEXT: addiw a2, a2, 819
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: slliw a0, a0, 2
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: srli a1, a0, 1
+; RV64ZBB-NEXT: lui a2, 349525
+; RV64ZBB-NEXT: addiw a2, a2, 1365
+; RV64ZBB-NEXT: and a1, a1, a2
+; RV64ZBB-NEXT: and a0, a0, a2
+; RV64ZBB-NEXT: slli a0, a0, 1
+; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srli a0, a0, 32
+; RV64ZBB-NEXT: ret
+ %tmp = call i32 @llvm.bitreverse.i32(i32 %a)
+ %tmp2 = call i32 @llvm.bswap.i32(i32 %tmp)
+ ret i32 %tmp2
+}
+
+define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind {
+; RV32I-LABEL: test_bitreverse_bswap_i64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a3, a1, 8
+; RV32I-NEXT: lui a2, 16
+; RV32I-NEXT: addi a2, a2, -256
+; RV32I-NEXT: and a3, a3, a2
+; RV32I-NEXT: srli a4, a1, 24
+; RV32I-NEXT: or a4, a3, a4
+; RV32I-NEXT: slli a5, a1, 8
+; RV32I-NEXT: lui a3, 4080
+; RV32I-NEXT: and a5, a5, a3
+; RV32I-NEXT: slli a1, a1, 24
+; RV32I-NEXT: or a1, a1, a5
+; RV32I-NEXT: or a1, a1, a4
+; RV32I-NEXT: srli a4, a1, 4
+; RV32I-NEXT: lui a5, 61681
+; RV32I-NEXT: addi a5, a5, -241
+; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: and a1, a1, a5
+; RV32I-NEXT: slli a1, a1, 4
+; RV32I-NEXT: or a1, a4, a1
+; RV32I-NEXT: srli a4, a1, 2
+; RV32I-NEXT: lui a6, 209715
+; RV32I-NEXT: addi a6, a6, 819
+; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: and a1, a1, a6
+; RV32I-NEXT: slli a1, a1, 2
+; RV32I-NEXT: or a1, a4, a1
+; RV32I-NEXT: srli a4, a1, 1
+; RV32I-NEXT: lui a7, 349525
+; RV32I-NEXT: addi a7, a7, 1365
+; RV32I-NEXT: and a4, a4, a7
+; RV32I-NEXT: and a1, a1, a7
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: or a1, a4, a1
+; RV32I-NEXT: srli a4, a0, 8
+; RV32I-NEXT: and a4, a4, a2
+; RV32I-NEXT: srli t0, a0, 24
+; RV32I-NEXT: or a4, a4, t0
+; RV32I-NEXT: slli t0, a0, 8
+; RV32I-NEXT: and t0, t0, a3
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a0, a0, t0
+; RV32I-NEXT: or a0, a0, a4
+; RV32I-NEXT: srli a4, a0, 4
+; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: and a0, a0, a5
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: srli a4, a0, 2
+; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: and a0, a0, a6
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: srli a4, a0, 1
+; RV32I-NEXT: and a4, a4, a7
+; RV32I-NEXT: and a0, a0, a7
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: srli a4, a0, 8
+; RV32I-NEXT: and a4, a4, a2
+; RV32I-NEXT: srli a5, a0, 24
+; RV32I-NEXT: or a4, a4, a5
+; RV32I-NEXT: slli a5, a0, 8
+; RV32I-NEXT: and a5, a5, a3
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a0, a0, a5
+; RV32I-NEXT: or a0, a0, a4
+; RV32I-NEXT: srli a4, a1, 8
+; RV32I-NEXT: and a2, a4, a2
+; RV32I-NEXT: srli a4, a1, 24
+; RV32I-NEXT: or a2, a2, a4
+; RV32I-NEXT: slli a4, a1, 8
+; RV32I-NEXT: and a3, a4, a3
+; RV32I-NEXT: slli a1, a1, 24
+; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_bitreverse_bswap_i64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srli a1, a0, 24
+; RV64I-NEXT: lui a2, 4080
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srli a3, a0, 8
+; RV64I-NEXT: li a4, 255
+; RV64I-NEXT: slli a5, a4, 24
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: or a1, a3, a1
+; RV64I-NEXT: srli a3, a0, 40
+; RV64I-NEXT: lui a6, 16
+; RV64I-NEXT: addiw a6, a6, -256
+; RV64I-NEXT: and a3, a3, a6
+; RV64I-NEXT: srli a7, a0, 56
+; RV64I-NEXT: or a3, a3, a7
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: slli a3, a0, 24
+; RV64I-NEXT: slli a7, a4, 40
+; RV64I-NEXT: and a3, a3, a7
+; RV64I-NEXT: srliw t0, a0, 24
+; RV64I-NEXT: slli t0, t0, 32
+; RV64I-NEXT: or a3, a3, t0
+; RV64I-NEXT: slli t0, a0, 40
+; RV64I-NEXT: slli a4, a4, 48
+; RV64I-NEXT: and t0, t0, a4
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: or a0, a0, t0
+; RV64I-NEXT: lui t0, %hi(.LCPI12_0)
+; RV64I-NEXT: ld t0, %lo(.LCPI12_0)(t0)
+; RV64I-NEXT: or a0, a0, a3
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: and a1, a1, t0
+; RV64I-NEXT: and a0, a0, t0
+; RV64I-NEXT: lui a3, %hi(.LCPI12_1)
+; RV64I-NEXT: ld a3, %lo(.LCPI12_1)(a3)
+; RV64I-NEXT: slli a0, a0, 4
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 2
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: lui a3, %hi(.LCPI12_2)
+; RV64I-NEXT: ld a3, %lo(.LCPI12_2)(a3)
+; RV64I-NEXT: slli a0, a0, 2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 1
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: srli a1, a0, 40
+; RV64I-NEXT: and a1, a1, a6
+; RV64I-NEXT: srli a3, a0, 56
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: srli a3, a0, 24
+; RV64I-NEXT: and a2, a3, a2
+; RV64I-NEXT: srli a3, a0, 8
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: or a2, a3, a2
+; RV64I-NEXT: or a1, a2, a1
+; RV64I-NEXT: slli a2, a0, 24
+; RV64I-NEXT: and a2, a2, a7
+; RV64I-NEXT: srliw a3, a0, 24
+; RV64I-NEXT: slli a3, a3, 32
+; RV64I-NEXT: or a2, a2, a3
+; RV64I-NEXT: slli a3, a0, 40
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: or a0, a0, a3
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV32ZBB-LABEL: test_bitreverse_bswap_i64:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: rev8 a1, a1
+; RV32ZBB-NEXT: srli a2, a1, 4
+; RV32ZBB-NEXT: lui a3, 61681
+; RV32ZBB-NEXT: addi a3, a3, -241
+; RV32ZBB-NEXT: and a2, a2, a3
+; RV32ZBB-NEXT: and a1, a1, a3
+; RV32ZBB-NEXT: slli a1, a1, 4
+; RV32ZBB-NEXT: or a1, a2, a1
+; RV32ZBB-NEXT: srli a2, a1, 2
+; RV32ZBB-NEXT: lui a4, 209715
+; RV32ZBB-NEXT: addi a4, a4, 819
+; RV32ZBB-NEXT: and a2, a2, a4
+; RV32ZBB-NEXT: and a1, a1, a4
+; RV32ZBB-NEXT: slli a1, a1, 2
+; RV32ZBB-NEXT: or a1, a2, a1
+; RV32ZBB-NEXT: srli a2, a1, 1
+; RV32ZBB-NEXT: lui a5, 349525
+; RV32ZBB-NEXT: addi a5, a5, 1365
+; RV32ZBB-NEXT: and a2, a2, a5
+; RV32ZBB-NEXT: and a1, a1, a5
+; RV32ZBB-NEXT: slli a1, a1, 1
+; RV32ZBB-NEXT: or a1, a2, a1
+; RV32ZBB-NEXT: rev8 a0, a0
+; RV32ZBB-NEXT: srli a2, a0, 4
+; RV32ZBB-NEXT: and a2, a2, a3
+; RV32ZBB-NEXT: and a0, a0, a3
+; RV32ZBB-NEXT: slli a0, a0, 4
+; RV32ZBB-NEXT: or a0, a2, a0
+; RV32ZBB-NEXT: srli a2, a0, 2
+; RV32ZBB-NEXT: and a2, a2, a4
+; RV32ZBB-NEXT: and a0, a0, a4
+; RV32ZBB-NEXT: slli a0, a0, 2
+; RV32ZBB-NEXT: or a0, a2, a0
+; RV32ZBB-NEXT: srli a2, a0, 1
+; RV32ZBB-NEXT: and a2, a2, a5
+; RV32ZBB-NEXT: and a0, a0, a5
+; RV32ZBB-NEXT: slli a0, a0, 1
+; RV32ZBB-NEXT: or a0, a2, a0
+; RV32ZBB-NEXT: rev8 a0, a0
+; RV32ZBB-NEXT: rev8 a1, a1
+; RV32ZBB-NEXT: ret
+;
+; RV64ZBB-LABEL: test_bitreverse_bswap_i64:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: lui a1, %hi(.LCPI12_0)
+; RV64ZBB-NEXT: ld a1, %lo(.LCPI12_0)(a1)
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srli a2, a0, 4
+; RV64ZBB-NEXT: and a2, a2, a1
+; RV64ZBB-NEXT: and a0, a0, a1
+; RV64ZBB-NEXT: lui a1, %hi(.LCPI12_1)
+; RV64ZBB-NEXT: ld a1, %lo(.LCPI12_1)(a1)
+; RV64ZBB-NEXT: slli a0, a0, 4
+; RV64ZBB-NEXT: or a0, a2, a0
+; RV64ZBB-NEXT: srli a2, a0, 2
+; RV64ZBB-NEXT: and a2, a2, a1
+; RV64ZBB-NEXT: and a0, a0, a1
+; RV64ZBB-NEXT: lui a1, %hi(.LCPI12_2)
+; RV64ZBB-NEXT: ld a1, %lo(.LCPI12_2)(a1)
+; RV64ZBB-NEXT: slli a0, a0, 2
+; RV64ZBB-NEXT: or a0, a2, a0
+; RV64ZBB-NEXT: srli a2, a0, 1
+; RV64ZBB-NEXT: and a2, a2, a1
+; RV64ZBB-NEXT: and a0, a0, a1
+; RV64ZBB-NEXT: slli a0, a0, 1
+; RV64ZBB-NEXT: or a0, a2, a0
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: ret
+ %tmp = call i64 @llvm.bitreverse.i64(i64 %a)
+ %tmp2 = call i64 @llvm.bswap.i64(i64 %tmp)
+ ret i64 %tmp2
+}
+
define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-LABEL: test_cttz_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a1, a0, 255
-; RV32I-NEXT: beqz a1, .LBB7_2
+; RV32I-NEXT: beqz a1, .LBB13_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
@@ -711,14 +1721,14 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: andi a0, a0, 15
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB7_2:
+; RV32I-NEXT: .LBB13_2:
; RV32I-NEXT: li a0, 8
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_cttz_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a0, 255
-; RV64I-NEXT: beqz a1, .LBB7_2
+; RV64I-NEXT: beqz a1, .LBB13_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
@@ -734,7 +1744,7 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 15
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB7_2:
+; RV64I-NEXT: .LBB13_2:
; RV64I-NEXT: li a0, 8
; RV64I-NEXT: ret
;
@@ -758,7 +1768,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srli a1, a1, 16
-; RV32I-NEXT: beqz a1, .LBB8_2
+; RV32I-NEXT: beqz a1, .LBB14_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
@@ -784,7 +1794,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: slli a0, a0, 19
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB8_2:
+; RV32I-NEXT: .LBB14_2:
; RV32I-NEXT: li a0, 16
; RV32I-NEXT: ret
;
@@ -792,7 +1802,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 48
; RV64I-NEXT: srli a1, a1, 48
-; RV64I-NEXT: beqz a1, .LBB8_2
+; RV64I-NEXT: beqz a1, .LBB14_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
@@ -818,7 +1828,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 51
; RV64I-NEXT: srli a0, a0, 59
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB8_2:
+; RV64I-NEXT: .LBB14_2:
; RV64I-NEXT: li a0, 16
; RV64I-NEXT: ret
;
@@ -842,7 +1852,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-LABEL: test_cttz_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: beqz a0, .LBB9_2
+; RV32I-NEXT: beqz a0, .LBB15_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -872,14 +1882,14 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB9_2:
+; RV32I-NEXT: .LBB15_2:
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_cttz_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a1, a0
-; RV64I-NEXT: beqz a1, .LBB9_2
+; RV64I-NEXT: beqz a1, .LBB15_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
@@ -909,7 +1919,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB9_2:
+; RV64I-NEXT: .LBB15_2:
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: ret
;
@@ -929,7 +1939,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-LABEL: test_ctlz_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: beqz a0, .LBB10_2
+; RV32I-NEXT: beqz a0, .LBB16_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -967,14 +1977,14 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB10_2:
+; RV32I-NEXT: .LBB16_2:
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_ctlz_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a1, a0
-; RV64I-NEXT: beqz a1, .LBB10_2
+; RV64I-NEXT: beqz a1, .LBB16_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
@@ -1012,7 +2022,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB10_2:
+; RV64I-NEXT: .LBB16_2:
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: ret
;
@@ -1082,14 +2092,14 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3 at plt
-; RV32I-NEXT: bnez s2, .LBB11_2
+; RV32I-NEXT: bnez s2, .LBB17_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
-; RV32I-NEXT: j .LBB11_3
-; RV32I-NEXT: .LBB11_2:
+; RV32I-NEXT: j .LBB17_3
+; RV32I-NEXT: .LBB17_2:
; RV32I-NEXT: srli a0, s0, 24
-; RV32I-NEXT: .LBB11_3:
+; RV32I-NEXT: .LBB17_3:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@@ -1104,49 +2114,49 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
;
; RV64I-LABEL: test_cttz_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: beqz a0, .LBB11_2
+; RV64I-NEXT: beqz a0, .LBB17_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: lui a1, %hi(.LCPI11_0)
-; RV64I-NEXT: ld a1, %lo(.LCPI11_0)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI11_1)
-; RV64I-NEXT: ld a2, %lo(.LCPI11_1)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI17_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI17_0)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI17_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI17_1)(a2)
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: lui a2, %hi(.LCPI11_2)
-; RV64I-NEXT: ld a2, %lo(.LCPI11_2)(a2)
+; RV64I-NEXT: lui a2, %hi(.LCPI17_2)
+; RV64I-NEXT: ld a2, %lo(.LCPI17_2)(a2)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: lui a1, %hi(.LCPI11_3)
-; RV64I-NEXT: ld a1, %lo(.LCPI11_3)(a1)
+; RV64I-NEXT: lui a1, %hi(.LCPI17_3)
+; RV64I-NEXT: ld a1, %lo(.LCPI17_3)(a1)
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB11_2:
+; RV64I-NEXT: .LBB17_2:
; RV64I-NEXT: li a0, 64
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_cttz_i64:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: bnez a0, .LBB11_2
+; RV32ZBB-NEXT: bnez a0, .LBB17_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: ctz a0, a1
; RV32ZBB-NEXT: addi a0, a0, 32
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
-; RV32ZBB-NEXT: .LBB11_2:
+; RV32ZBB-NEXT: .LBB17_2:
; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
@@ -1404,14 +2414,14 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3 at plt
-; RV32I-NEXT: bnez s2, .LBB15_2
+; RV32I-NEXT: bnez s2, .LBB21_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
-; RV32I-NEXT: j .LBB15_3
-; RV32I-NEXT: .LBB15_2:
+; RV32I-NEXT: j .LBB21_3
+; RV32I-NEXT: .LBB21_2:
; RV32I-NEXT: srli a0, s0, 24
-; RV32I-NEXT: .LBB15_3:
+; RV32I-NEXT: .LBB21_3:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@@ -1431,24 +2441,24 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: lui a1, %hi(.LCPI15_0)
-; RV64I-NEXT: ld a1, %lo(.LCPI15_0)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI15_1)
-; RV64I-NEXT: ld a2, %lo(.LCPI15_1)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI21_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI21_0)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI21_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI21_1)(a2)
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: lui a2, %hi(.LCPI15_2)
-; RV64I-NEXT: ld a2, %lo(.LCPI15_2)(a2)
+; RV64I-NEXT: lui a2, %hi(.LCPI21_2)
+; RV64I-NEXT: ld a2, %lo(.LCPI21_2)(a2)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: lui a1, %hi(.LCPI15_3)
-; RV64I-NEXT: ld a1, %lo(.LCPI15_3)(a1)
+; RV64I-NEXT: lui a1, %hi(.LCPI21_3)
+; RV64I-NEXT: ld a1, %lo(.LCPI21_3)(a1)
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -1457,13 +2467,13 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
;
; RV32ZBB-LABEL: test_cttz_i64_zero_undef:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: bnez a0, .LBB15_2
+; RV32ZBB-NEXT: bnez a0, .LBB21_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: ctz a0, a1
; RV32ZBB-NEXT: addi a0, a0, 32
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
-; RV32ZBB-NEXT: .LBB15_2:
+; RV32ZBB-NEXT: .LBB21_2:
; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
@@ -1608,24 +2618,24 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a1, %hi(.LCPI17_0)
-; RV64I-NEXT: ld a1, %lo(.LCPI17_0)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI17_1)
-; RV64I-NEXT: ld a2, %lo(.LCPI17_1)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI23_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI23_0)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI23_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI23_1)(a2)
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: lui a2, %hi(.LCPI17_2)
-; RV64I-NEXT: ld a2, %lo(.LCPI17_2)(a2)
+; RV64I-NEXT: lui a2, %hi(.LCPI23_2)
+; RV64I-NEXT: ld a2, %lo(.LCPI23_2)(a2)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: lui a1, %hi(.LCPI17_3)
-; RV64I-NEXT: ld a1, %lo(.LCPI17_3)(a1)
+; RV64I-NEXT: lui a1, %hi(.LCPI23_3)
+; RV64I-NEXT: ld a1, %lo(.LCPI23_3)(a1)
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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