[llvm] f69379d - [InstCombine] Add test coverage for PR48683

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Sun Jan 23 10:03:54 PST 2022


Author: Simon Pilgrim
Date: 2022-01-23T18:03:17Z
New Revision: f69379d0a43bbe14e58e45286de3ae1cf8a58147

URL: https://github.com/llvm/llvm-project/commit/f69379d0a43bbe14e58e45286de3ae1cf8a58147
DIFF: https://github.com/llvm/llvm-project/commit/f69379d0a43bbe14e58e45286de3ae1cf8a58147.diff

LOG: [InstCombine] Add test coverage for PR48683

D108992 added self-multiply handling to KnownBits::mul but we don't use it yet..

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/mul-masked-bits.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/mul-masked-bits.ll b/llvm/test/Transforms/InstCombine/mul-masked-bits.ll
index fcff725cdf6f1..4886cd581a284 100644
--- a/llvm/test/Transforms/InstCombine/mul-masked-bits.ll
+++ b/llvm/test/Transforms/InstCombine/mul-masked-bits.ll
@@ -1,10 +1,10 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @foo(i32 %x, i32 %y) {
 ; CHECK-LABEL: @foo(
-; CHECK-NEXT:    [[A:%.*]] = and i32 %x, 7
-; CHECK-NEXT:    [[B:%.*]] = and i32 %y, 7
+; CHECK-NEXT:    [[A:%.*]] = and i32 [[X:%.*]], 7
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[Y:%.*]], 7
 ; CHECK-NEXT:    [[C:%.*]] = mul nuw nsw i32 [[A]], [[B]]
 ; CHECK-NEXT:    [[D:%.*]] = shl nuw i32 [[C]], 26
 ; CHECK-NEXT:    [[E:%.*]] = ashr exact i32 [[D]], 26
@@ -17,3 +17,44 @@ define i32 @foo(i32 %x, i32 %y) {
   %e = ashr i32 %d, 26
   ret i32 %e
 }
+
+; PR48683 'Quadratic Reciprocity' - and(mul(x,x),2) -> 0
+
+define i1 @PR48683(i32 %x) {
+; CHECK-LABEL: @PR48683(
+; CHECK-NEXT:    [[A:%.*]] = mul i32 [[X:%.*]], [[X]]
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[A]], 2
+; CHECK-NEXT:    [[C:%.*]] = icmp ne i32 [[B]], 0
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = mul i32 %x, %x
+  %b = and i32 %a, 2
+  %c = icmp ne i32 %b, 0
+  ret i1 %c
+}
+
+define <4 x i1> @PR48683_vec(<4 x i32> %x) {
+; CHECK-LABEL: @PR48683_vec(
+; CHECK-NEXT:    [[A:%.*]] = mul <4 x i32> [[X:%.*]], [[X]]
+; CHECK-NEXT:    [[B:%.*]] = and <4 x i32> [[A]], <i32 2, i32 2, i32 2, i32 2>
+; CHECK-NEXT:    [[C:%.*]] = icmp ne <4 x i32> [[B]], zeroinitializer
+; CHECK-NEXT:    ret <4 x i1> [[C]]
+;
+  %a = mul <4 x i32> %x, %x
+  %b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 2>
+  %c = icmp ne <4 x i32> %b, zeroinitializer
+  ret <4 x i1> %c
+}
+
+define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) {
+; CHECK-LABEL: @PR48683_vec_undef(
+; CHECK-NEXT:    [[A:%.*]] = mul <4 x i32> [[X:%.*]], [[X]]
+; CHECK-NEXT:    [[B:%.*]] = and <4 x i32> [[A]], <i32 2, i32 2, i32 2, i32 undef>
+; CHECK-NEXT:    [[C:%.*]] = icmp ne <4 x i32> [[B]], zeroinitializer
+; CHECK-NEXT:    ret <4 x i1> [[C]]
+;
+  %a = mul <4 x i32> %x, %x
+  %b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 undef>
+  %c = icmp ne <4 x i32> %b, zeroinitializer
+  ret <4 x i1> %c
+}


        


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