[PATCH] D117975: [JITLink][RISCV] fix the extractBits behavior and add R_RISCV_JAL relocation.

[luxufan via Phabricator via llvm-commits]

StephenFan added inline comments.


================
Comment at: llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp:230
+      }
+      uint32_t Hi = Value >> 12;
+      uint32_t Imm20 = extractBits(Hi, 20, 1) << 31;
----------------
I think `R_RISCV_JAL` don't need to left shift `Value` 12 bits. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117975/new/

https://reviews.llvm.org/D117975