[PATCH] D117954: [RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub.

[Yueh-Ting Chen via Phabricator via llvm-commits]

eopXD added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7306
+  unsigned VOpc;
+  switch (N->getOpcode()) {
+  default: llvm_unreachable("Unexpected opcode");
----------------
craig.topper wrote:
> eopXD wrote:
> > Why not just directly fetch with getOpCode and have assertions in the beginning of the function just like the previous one?
> I don't think I understand the question. This switch mainly exists to convert from one opcode to another.
I misread the code. I thought it was just direct copying. My bad.


Repository:
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  https://reviews.llvm.org/D117954/new/

https://reviews.llvm.org/D117954