[PATCH] D117452: [RISCV] Provide VLOperand in td.

[Han-Kuan Chen via Phabricator via llvm-commits]

HanKuanChen created this revision.
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Currently, users expected VL is the last operand. However, since some

intrinsics has tail policy in the last operand, this rule cannot be used

anymore.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117452

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll

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