[llvm] 5a45778 - [RISCV] Add patterns for vector widening integer multiply-add instructions
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 16 18:37:18 PST 2022
Author: eopXD
Date: 2022-01-16T18:37:13-08:00
New Revision: 5a457782a26e82033379b7d92846ab6648f453e4
URL: https://github.com/llvm/llvm-project/commit/5a457782a26e82033379b7d92846ab6648f453e4
DIFF: https://github.com/llvm/llvm-project/commit/5a457782a26e82033379b7d92846ab6648f453e4.diff
LOG: [RISCV] Add patterns for vector widening integer multiply-add instructions
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117404
Added:
llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index c2821306043d0..c52312bfabbed 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -388,6 +388,31 @@ multiclass VPatWidenBinarySDNode_VV_VX_WV_WX<SDNode op, PatFrags extop, string i
}
}
+multiclass VPatWidenMulAddSDNode_VV<PatFrags extop1, PatFrags extop2, string instruction_name> {
+ foreach vti = AllWidenableIntVectors in {
+ def : Pat<
+ (add (vti.Wti.Vector vti.Wti.RegClass:$rd),
+ (mul_oneuse (vti.Wti.Vector (extop1 (vti.Vti.Vector vti.Vti.RegClass:$rs1))),
+ (vti.Wti.Vector (extop2 (vti.Vti.Vector vti.Vti.RegClass:$rs2))))),
+ (!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
+ vti.Wti.RegClass:$rd, vti.Vti.RegClass:$rs1, vti.Vti.RegClass:$rs2,
+ vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC
+ )>;
+ }
+}
+multiclass VPatWidenMulAddSDNode_VX<PatFrags extop1, PatFrags extop2, string instruction_name> {
+ foreach vti = AllWidenableIntVectors in {
+ def : Pat<
+ (add (vti.Wti.Vector vti.Wti.RegClass:$rd),
+ (mul_oneuse (vti.Wti.Vector (extop1 (vti.Vti.Vector (SplatPat GPR:$rs1)))),
+ (vti.Wti.Vector (extop2 (vti.Vti.Vector vti.Vti.RegClass:$rs2))))),
+ (!cast<Instruction>(instruction_name#"_VX_"#vti.Vti.LMul.MX)
+ vti.Wti.RegClass:$rd, GPR:$rs1, vti.Vti.RegClass:$rs2,
+ vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC
+ )>;
+ }
+}
+
//===----------------------------------------------------------------------===//
// Patterns.
//===----------------------------------------------------------------------===//
@@ -547,6 +572,15 @@ foreach vti = AllIntegerVectors in {
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
+// 12.14 Vector Widening Integer Multiply-Add Instructions
+defm : VPatWidenMulAddSDNode_VV<sext_oneuse, sext_oneuse, "PseudoVWMACC">;
+defm : VPatWidenMulAddSDNode_VX<sext_oneuse, sext_oneuse, "PseudoVWMACC">;
+defm : VPatWidenMulAddSDNode_VV<zext_oneuse, zext_oneuse, "PseudoVWMACCU">;
+defm : VPatWidenMulAddSDNode_VX<zext_oneuse, zext_oneuse, "PseudoVWMACCU">;
+defm : VPatWidenMulAddSDNode_VV<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">;
+defm : VPatWidenMulAddSDNode_VX<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">;
+defm : VPatWidenMulAddSDNode_VX<zext_oneuse, sext_oneuse, "PseudoVWMACCUS">;
+
// 12.15. Vector Integer Merge Instructions
foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (vselect (vti.Mask V0), vti.RegClass:$rs1,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
new file mode 100644
index 0000000000000..fdc1bd7364120
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
@@ -0,0 +1,457 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
+; CHECK-LABEL: vwmacc_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwmacc.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+
+ %x = mul <vscale x 1 x i64> %vd, %ve
+ %y = add <vscale x 1 x i64> %x, %vc
+ ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 1 x i64> @vwmacc_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
+; CHECK-LABEL: vwmacc_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwmacc.vx v9, a0, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+
+ %x = mul <vscale x 1 x i64> %vd, %ve
+ %y = add <vscale x 1 x i64> %x, %vc
+ ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 1 x i64> @vwmaccu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
+; CHECK-LABEL: vwmaccu_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwmaccu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %ve = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+
+ %x = mul <vscale x 1 x i64> %vd, %ve
+ %y = add <vscale x 1 x i64> %x, %vc
+ ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 1 x i64> @vwmaccu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
+; CHECK-LABEL: vwmaccu_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwmaccu.vx v9, a0, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+
+ %x = mul <vscale x 1 x i64> %vd, %ve
+ %y = add <vscale x 1 x i64> %x, %vc
+ ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 1 x i64> @vwmaccsu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
+; CHECK-LABEL: vwmaccsu_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwmaccsu.vv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+
+ %x = mul <vscale x 1 x i64> %vd, %ve
+ %y = add <vscale x 1 x i64> %x, %vc
+ ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 1 x i64> @vwmaccsu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
+; CHECK-LABEL: vwmaccsu_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwmaccsu.vx v9, a0, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+
+ %x = mul <vscale x 1 x i64> %vd, %ve
+ %y = add <vscale x 1 x i64> %x, %vc
+ ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 1 x i64> @vwmaccus_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
+; CHECK-LABEL: vwmaccus_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwmaccus.vx v9, a0, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+
+ %x = mul <vscale x 1 x i64> %vd, %ve
+ %y = add <vscale x 1 x i64> %x, %vc
+ ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 2 x i64> @vwmacc_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {
+; CHECK-LABEL: vwmacc_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwmacc.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+
+ %x = mul <vscale x 2 x i64> %vd, %ve
+ %y = add <vscale x 2 x i64> %x, %vc
+ ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 2 x i64> @vwmacc_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
+; CHECK-LABEL: vwmacc_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwmacc.vx v10, a0, v8
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+
+ %x = mul <vscale x 2 x i64> %vd, %ve
+ %y = add <vscale x 2 x i64> %x, %vc
+ ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 2 x i64> @vwmaccu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {
+; CHECK-LABEL: vwmaccu_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwmaccu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %ve = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+
+ %x = mul <vscale x 2 x i64> %vd, %ve
+ %y = add <vscale x 2 x i64> %x, %vc
+ ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 2 x i64> @vwmaccu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
+; CHECK-LABEL: vwmaccu_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwmaccu.vx v10, a0, v8
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+
+ %x = mul <vscale x 2 x i64> %vd, %ve
+ %y = add <vscale x 2 x i64> %x, %vc
+ ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 2 x i64> @vwmaccsu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {
+; CHECK-LABEL: vwmaccsu_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwmaccsu.vv v10, v9, v8
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+
+ %x = mul <vscale x 2 x i64> %vd, %ve
+ %y = add <vscale x 2 x i64> %x, %vc
+ ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 2 x i64> @vwmaccsu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
+; CHECK-LABEL: vwmaccsu_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwmaccsu.vx v10, a0, v8
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+
+ %x = mul <vscale x 2 x i64> %vd, %ve
+ %y = add <vscale x 2 x i64> %x, %vc
+ ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 2 x i64> @vwmaccus_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
+; CHECK-LABEL: vwmaccus_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwmaccus.vx v10, a0, v8
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+
+ %x = mul <vscale x 2 x i64> %vd, %ve
+ %y = add <vscale x 2 x i64> %x, %vc
+ ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 4 x i64> @vwmacc_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {
+; CHECK-LABEL: vwmacc_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwmacc.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+
+ %x = mul <vscale x 4 x i64> %vd, %ve
+ %y = add <vscale x 4 x i64> %x, %vc
+ ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 4 x i64> @vwmacc_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
+; CHECK-LABEL: vwmacc_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwmacc.vx v12, a0, v8
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+
+ %x = mul <vscale x 4 x i64> %vd, %ve
+ %y = add <vscale x 4 x i64> %x, %vc
+ ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 4 x i64> @vwmaccu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {
+; CHECK-LABEL: vwmaccu_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwmaccu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %ve = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+
+ %x = mul <vscale x 4 x i64> %vd, %ve
+ %y = add <vscale x 4 x i64> %x, %vc
+ ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 4 x i64> @vwmaccu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
+; CHECK-LABEL: vwmaccu_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwmaccu.vx v12, a0, v8
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+
+ %x = mul <vscale x 4 x i64> %vd, %ve
+ %y = add <vscale x 4 x i64> %x, %vc
+ ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 4 x i64> @vwmaccsu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {
+; CHECK-LABEL: vwmaccsu_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwmaccsu.vv v12, v10, v8
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+
+ %x = mul <vscale x 4 x i64> %vd, %ve
+ %y = add <vscale x 4 x i64> %x, %vc
+ ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 4 x i64> @vwmaccsu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
+; CHECK-LABEL: vwmaccsu_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwmaccsu.vx v12, a0, v8
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+
+ %x = mul <vscale x 4 x i64> %vd, %ve
+ %y = add <vscale x 4 x i64> %x, %vc
+ ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 4 x i64> @vwmaccus_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
+; CHECK-LABEL: vwmaccus_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwmaccus.vx v12, a0, v8
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+
+ %x = mul <vscale x 4 x i64> %vd, %ve
+ %y = add <vscale x 4 x i64> %x, %vc
+ ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 8 x i64> @vwmacc_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {
+; CHECK-LABEL: vwmacc_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwmacc.vv v16, v8, v12
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+
+ %x = mul <vscale x 8 x i64> %vd, %ve
+ %y = add <vscale x 8 x i64> %x, %vc
+ ret <vscale x 8 x i64> %y
+}
+
+define <vscale x 8 x i64> @vwmacc_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
+; CHECK-LABEL: vwmacc_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwmacc.vx v16, a0, v8
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+
+ %x = mul <vscale x 8 x i64> %vd, %ve
+ %y = add <vscale x 8 x i64> %x, %vc
+ ret <vscale x 8 x i64> %y
+}
+
+define <vscale x 8 x i64> @vwmaccu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {
+; CHECK-LABEL: vwmaccu_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwmaccu.vv v16, v8, v12
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %ve = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+
+ %x = mul <vscale x 8 x i64> %vd, %ve
+ %y = add <vscale x 8 x i64> %x, %vc
+ ret <vscale x 8 x i64> %y
+}
+
+define <vscale x 8 x i64> @vwmaccu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
+; CHECK-LABEL: vwmaccu_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwmaccu.vx v16, a0, v8
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+
+ %x = mul <vscale x 8 x i64> %vd, %ve
+ %y = add <vscale x 8 x i64> %x, %vc
+ ret <vscale x 8 x i64> %y
+}
+
+define <vscale x 8 x i64> @vwmaccsu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {
+; CHECK-LABEL: vwmaccsu_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwmaccsu.vv v16, v12, v8
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+
+ %x = mul <vscale x 8 x i64> %vd, %ve
+ %y = add <vscale x 8 x i64> %x, %vc
+ ret <vscale x 8 x i64> %y
+}
+
+define <vscale x 8 x i64> @vwmaccsu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
+; CHECK-LABEL: vwmaccsu_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwmaccsu.vx v16, a0, v8
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+
+ %x = mul <vscale x 8 x i64> %vd, %ve
+ %y = add <vscale x 8 x i64> %x, %vc
+ ret <vscale x 8 x i64> %y
+}
+
+define <vscale x 8 x i64> @vwmaccus_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
+; CHECK-LABEL: vwmaccus_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwmaccus.vx v16, a0, v8
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+
+ %x = mul <vscale x 8 x i64> %vd, %ve
+ %y = add <vscale x 8 x i64> %x, %vc
+ ret <vscale x 8 x i64> %y
+}
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