[PATCH] D115419: [PowerPC] Allow absolute expressions in relocations

[ChenZheng via Phabricator via llvm-commits]

shchenz added a comment.

Maybe I am misunderstanding the relocation fixups and DQ form instructions, if so, please ignore my comments. : )



================
Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp:47
   case PPC::fixup_ppc_half16ds:
+  case PPC::fixup_ppc_half16dq:
     return Value & 0xfffc;
----------------
For DQ form the adjusted value should be `Value & 0xfff0`? The last 4 bits are 0?


================
Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h:54
 
+  /// A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for
+  /// instrs like 'lxv'. Produces the same relocation as fixup_ppc_half16ds.
----------------
For DQ form, the fixup(DQ field?) should be 12 bits and 4 implied zero bits?


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https://reviews.llvm.org/D115419