[PATCH] D117003: [SchedModels][CortexA55] Add ASIMD integer instructioins

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I'm not sure how much I love the predicate matching in the scheduler, as opposed to just matching instructions opcodes. There are quite a few instructions which narrow or enlarge vectorsm where register types are misleading.

Can you at least move the code so it doesn't look like this is bolted onto the end of the existing schedule :)
The SchedWriteRes should live near the other SchedWriteRes, and only the instruction definitions should be with the other instructions, etc.



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Comment at: llvm/lib/Target/AArch64/AArch64SchedA55.td:380
+  let ResourceCycles = rcl;
+  let EndGroup = 1;
+}
----------------
"01" in the dual issue tables means it must be the first item (slot 0). "10" would be EndGroup, and is mostly limited to certains branches and rets.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedA55.td:494
+// COPY
+def : InstRW<[CortexA55WriteCOPY], (instrs COPY)>;
 }
----------------
Does this add a lot? It's not really how COPYs work.


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Comment at: llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s:2506
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     2.00    -      -     ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
-# CHECK-NEXT:  -      -      -      -     0.50   0.50    -      -      -      -      -      -     mla	v0.8b, v0.8b, v0.8b
-# CHECK-NEXT:  -      -      -      -     0.50   0.50    -      -      -      -      -      -     mls	v0.4h, v0.4h, v0.4h
+# CHECK-NEXT:  -      -      -      -      -      -      -     0.50   0.50    -      -      -     mla	v0.8b, v0.8b, v0.8b
+# CHECK-NEXT:  -      -      -      -      -      -      -     0.50   0.50    -      -      -     mls	v0.4h, v0.4h, v0.4h
----------------
What is the reasoning for the integer multiplies going down the FPMAC pipeline?


Repository:
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  https://reviews.llvm.org/D117003/new/

https://reviews.llvm.org/D117003