[PATCH] D117404: [RISCV] Add patterns for vector widening integer multiply-add instructions
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 16 00:54:09 PST 2022
craig.topper added inline comments.
Herald added a subscriber: alextsao1999.
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:555
+ (add (vti.Wti.Vector vti.Wti.RegClass:$rd),
+ (mul_oneuse (vti.Wti.Vector (extop1 (vti.Vti.Vector vti.Vti.RegClass:$rs1))),
+ (vti.Wti.Vector (extop2 (vti.Vti.Vector vti.Vti.RegClass:$rs2))))),
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Indent this at least one more space so that its more clear that its nested under the `add`.
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:558
+ (!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
+ vti.Wti.RegClass:$rd, vti.Vti.RegClass:$rs1, vti.Vti.RegClass:$rs2,
+ vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC
----------------
Indent this one more space.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D117404/new/
https://reviews.llvm.org/D117404
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