[llvm] 4c1e1e0 - [RISCV] Add RISCVISD::BFPW to ComputeNumSignBitsForTargetNode.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-01-15T15:23:49-08:00
New Revision: 4c1e1e05cb901a2ed9055e5d6ac6ce60b826a288

URL: https://github.com/llvm/llvm-project/commit/4c1e1e05cb901a2ed9055e5d6ac6ce60b826a288
DIFF: https://github.com/llvm/llvm-project/commit/4c1e1e05cb901a2ed9055e5d6ac6ce60b826a288.diff

LOG: [RISCV] Add RISCVISD::BFPW to ComputeNumSignBitsForTargetNode.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index fe1a71f7fc768..6c628aad8d69e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7964,6 +7964,7 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
   case RISCVISD::UNSHFLW:
   case RISCVISD::BCOMPRESSW:
   case RISCVISD::BDECOMPRESSW:
+  case RISCVISD::BFPW:
   case RISCVISD::FCVT_W_RV64:
   case RISCVISD::FCVT_WU_RV64:
   case RISCVISD::STRICT_FCVT_W_RV64:

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
index ce1e6131cdea5..735810bfa45ed 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
@@ -4,7 +4,7 @@
 
 declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
 
-define i32 @bfp32(i32 %a, i32 %b) nounwind {
+define signext i32 @bfp32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64ZBF-LABEL: bfp32:
 ; RV64ZBF:       # %bb.0:
 ; RV64ZBF-NEXT:    bfpw a0, a0, a1