[PATCH] D117302: [InstCombine] Simplify addends reordering logic

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

I can't tell if this has a greater effect than shown by the test diff. That diff actually demonstrates a basic missing canonicalization in IR - no fast-math is needed to convert fsub to fadd in that example or any of these more general cases:

  define float @fmul_c1(float %x, float %y) {
    %m = fmul float %x, 7.000000e+00
    %r = fsub float %y, %m
    ret float %r
  }
  
  define float @fdiv_c0(float %x, float %y) {
    %m = fdiv float 7.000000e+00, %x
    %r = fsub float %y, %m
    ret float %r
  }
  
  define float @fdiv_c1(float %x, float %y) {
    %m = fdiv float %x, 7.000000e+00
    %r = fsub float %y, %m
    ret float %r
  }

We do have this transform in the backend though (pushing the implicit negation op into the constant operand). For example, if you codegen this with llc for x86, you'll see 3 "addss" instructions and no "subss". Would adding those canonicalizations to IR solve your motivating case(s)? 
Or is there a larger example of a change resulting from this patch?


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  https://reviews.llvm.org/D117302/new/

https://reviews.llvm.org/D117302