[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Jianjian Guan via Phabricator via llvm-commits]

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Now the backend promotes mask vector to an i8 vector and extract element from that. We could bitcast to a widen element vector, and extract from it to GPR, then use I instruction to extract the certain bit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117389

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

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