[llvm] b148348 - [RISCV] Add patterns for vector widening integer add/subtract
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 14 18:21:39 PST 2022
Author: jacquesguan
Date: 2022-01-15T09:41:07+08:00
New Revision: b148348ad4863a78c5f1737c122dbc3026063aa6
URL: https://github.com/llvm/llvm-project/commit/b148348ad4863a78c5f1737c122dbc3026063aa6
DIFF: https://github.com/llvm/llvm-project/commit/b148348ad4863a78c5f1737c122dbc3026063aa6.diff
LOG: [RISCV] Add patterns for vector widening integer add/subtract
Add patterns for vector widening integer add/subtract instructions
Differential Revision: https://reviews.llvm.org/D117188
Added:
llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 9a61ec2f51db..8be7132dbd9a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1034,6 +1034,18 @@ def mul_const_oneuse : PatFrag<(ops node:$A, node:$B),
return false;
}]>;
+def sext_oneuse : PatFrag<(ops node:$A), (sext node:$A), [{
+ return N->hasOneUse();
+}]>;
+
+def zext_oneuse : PatFrag<(ops node:$A), (zext node:$A), [{
+ return N->hasOneUse();
+}]>;
+
+def anyext_oneuse : PatFrag<(ops node:$A), (anyext node:$A), [{
+ return N->hasOneUse();
+}]>;
+
/// Simple arithmetic operations
def : PatGprGpr<add, ADD>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 711ad4335ece..c2821306043d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -363,6 +363,31 @@ multiclass VPatNConvertFP2ISDNode_V<SDNode vop, string instruction_name> {
}
}
+multiclass VPatWidenBinarySDNode_VV_VX_WV_WX<SDNode op, PatFrags extop, string instruction_name> {
+ foreach vti = AllWidenableIntVectors in {
+ def : Pat<(op (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
+ (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
+ (!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
+ vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
+ vti.Vti.AVL, vti.Vti.Log2SEW)>;
+ def : Pat<(op (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
+ (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
+ (!cast<Instruction>(instruction_name#"_VX_"#vti.Vti.LMul.MX)
+ vti.Vti.RegClass:$rs2, GPR:$rs1,
+ vti.Vti.AVL, vti.Vti.Log2SEW)>;
+ def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+ (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
+ (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
+ vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
+ vti.Vti.AVL, vti.Vti.Log2SEW)>;
+ def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+ (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
+ (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX)
+ vti.Wti.RegClass:$rs2, GPR:$rs1,
+ vti.Vti.AVL, vti.Vti.Log2SEW)>;
+ }
+}
+
//===----------------------------------------------------------------------===//
// Patterns.
//===----------------------------------------------------------------------===//
@@ -399,6 +424,15 @@ foreach vti = AllIntegerVectors in {
vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>;
}
+// 12.2. Vector Widening Integer Add and Subtract
+defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">;
+defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">;
+defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">;
+
+defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, sext_oneuse, "PseudoVWSUB">;
+defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, zext_oneuse, "PseudoVWSUBU">;
+defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, anyext_oneuse, "PseudoVWSUBU">;
+
// 12.3. Vector Integer Extension
defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2",
AllFractionableVF2IntVectors>;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
new file mode 100644
index 000000000000..54dbaf8a52d3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
@@ -0,0 +1,427 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i64> @vwadd_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vwadd_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %ve = add <vscale x 1 x i64> %vc, %vd
+ ret <vscale x 1 x i64> %ve
+}
+
+define <vscale x 1 x i64> @vwaddu_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vwaddu_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %ve = add <vscale x 1 x i64> %vc, %vd
+ ret <vscale x 1 x i64> %ve
+}
+
+define <vscale x 1 x i64> @vwadd_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vwadd_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+ %ve = add <vscale x 1 x i64> %vc, %vd
+ ret <vscale x 1 x i64> %ve
+}
+
+define <vscale x 1 x i64> @vwaddu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vwaddu_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+ %ve = add <vscale x 1 x i64> %vc, %vd
+ ret <vscale x 1 x i64> %ve
+}
+
+define <vscale x 1 x i64> @vwadd_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vwadd_wv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwadd.wv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %vd = add <vscale x 1 x i64> %va, %vc
+ ret <vscale x 1 x i64> %vd
+}
+
+define <vscale x 1 x i64> @vwaddu_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vwaddu_wv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwaddu.wv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %vd = add <vscale x 1 x i64> %va, %vc
+ ret <vscale x 1 x i64> %vd
+}
+
+define <vscale x 1 x i64> @vwadd_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vwadd_wx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwadd.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+ %vc = add <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vwaddu_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vwaddu_wx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vwaddu.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+ %vc = add <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vwadd_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vwadd_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %ve = add <vscale x 2 x i64> %vc, %vd
+ ret <vscale x 2 x i64> %ve
+}
+
+define <vscale x 2 x i64> @vwaddu_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vwaddu_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %ve = add <vscale x 2 x i64> %vc, %vd
+ ret <vscale x 2 x i64> %ve
+}
+
+define <vscale x 2 x i64> @vwadd_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vwadd_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwadd.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %ve = add <vscale x 2 x i64> %vc, %vd
+ ret <vscale x 2 x i64> %ve
+}
+
+define <vscale x 2 x i64> @vwaddu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vwaddu_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwaddu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %ve = add <vscale x 2 x i64> %vc, %vd
+ ret <vscale x 2 x i64> %ve
+}
+
+define <vscale x 2 x i64> @vwadd_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vwadd_wv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwadd.wv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %vd = add <vscale x 2 x i64> %va, %vc
+ ret <vscale x 2 x i64> %vd
+}
+
+define <vscale x 2 x i64> @vwaddu_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vwaddu_wv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwaddu.wv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %vd = add <vscale x 2 x i64> %va, %vc
+ ret <vscale x 2 x i64> %vd
+}
+
+define <vscale x 2 x i64> @vwadd_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vwadd_wx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwadd.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %vc = add <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vwaddu_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vwaddu_wx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vwaddu.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %vc = add <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vwadd_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vwadd_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %ve = add <vscale x 4 x i64> %vc, %vd
+ ret <vscale x 4 x i64> %ve
+}
+
+define <vscale x 4 x i64> @vwaddu_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vwaddu_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %ve = add <vscale x 4 x i64> %vc, %vd
+ ret <vscale x 4 x i64> %ve
+}
+
+define <vscale x 4 x i64> @vwadd_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vwadd_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwadd.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+ %ve = add <vscale x 4 x i64> %vc, %vd
+ ret <vscale x 4 x i64> %ve
+}
+
+define <vscale x 4 x i64> @vwaddu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vwaddu_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwaddu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+ %ve = add <vscale x 4 x i64> %vc, %vd
+ ret <vscale x 4 x i64> %ve
+}
+
+define <vscale x 4 x i64> @vwadd_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vwadd_wv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwadd.wv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %vd = add <vscale x 4 x i64> %va, %vc
+ ret <vscale x 4 x i64> %vd
+}
+
+define <vscale x 4 x i64> @vwaddu_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vwaddu_wv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwaddu.wv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %vd = add <vscale x 4 x i64> %va, %vc
+ ret <vscale x 4 x i64> %vd
+}
+
+define <vscale x 4 x i64> @vwadd_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vwadd_wx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwadd.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+ %vc = add <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vwaddu_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vwaddu_wx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vwaddu.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+ %vc = add <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vwadd_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vwadd_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwadd.vv v16, v8, v12
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %ve = add <vscale x 8 x i64> %vc, %vd
+ ret <vscale x 8 x i64> %ve
+}
+
+define <vscale x 8 x i64> @vwaddu_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vwaddu_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwaddu.vv v16, v8, v12
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %ve = add <vscale x 8 x i64> %vc, %vd
+ ret <vscale x 8 x i64> %ve
+}
+
+define <vscale x 8 x i64> @vwadd_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vwadd_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwadd.vx v16, v8, a0
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+ %ve = add <vscale x 8 x i64> %vc, %vd
+ ret <vscale x 8 x i64> %ve
+}
+
+define <vscale x 8 x i64> @vwaddu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vwaddu_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwaddu.vx v16, v8, a0
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+ %ve = add <vscale x 8 x i64> %vc, %vd
+ ret <vscale x 8 x i64> %ve
+}
+
+define <vscale x 8 x i64> @vwadd_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vwadd_wv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwadd.wv v24, v8, v16
+; CHECK-NEXT: vmv8r.v v8, v24
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %vd = add <vscale x 8 x i64> %va, %vc
+ ret <vscale x 8 x i64> %vd
+}
+
+define <vscale x 8 x i64> @vwaddu_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vwaddu_wv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwaddu.wv v24, v8, v16
+; CHECK-NEXT: vmv8r.v v8, v24
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %vd = add <vscale x 8 x i64> %va, %vc
+ ret <vscale x 8 x i64> %vd
+}
+
+define <vscale x 8 x i64> @vwadd_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vwadd_wx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwadd.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+ %vc = add <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vwaddu_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vwaddu_wx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vwaddu.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+ %vc = add <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
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