[PATCH] D117378: [RISCV] [NFC] Use macro to reduce repetive switch cases

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng updated this revision to Diff 400220.
Chenbing.Zheng added a comment.

modify CASE_EXTEND_TWO_OPERAND to CASE_EXTEND_TWO_OPERANDS


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117378/new/

https://reviews.llvm.org/D117378

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp


Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6229,20 +6229,6 @@
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       return;
     }
-    case Intrinsic::riscv_grev:
-    case Intrinsic::riscv_gorc: {
-      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
-             "Unexpected custom legalisation");
-      SDValue NewOp1 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue NewOp2 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
-      unsigned Opc =
-          IntNo == Intrinsic::riscv_grev ? RISCVISD::GREVW : RISCVISD::GORCW;
-      SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
-      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
-      break;
-    }
     case Intrinsic::riscv_shfl:
     case Intrinsic::riscv_unshfl: {
       assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
@@ -6263,32 +6249,6 @@
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       break;
     }
-    case Intrinsic::riscv_bcompress:
-    case Intrinsic::riscv_bdecompress: {
-      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
-             "Unexpected custom legalisation");
-      SDValue NewOp1 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue NewOp2 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
-      unsigned Opc = IntNo == Intrinsic::riscv_bcompress
-                         ? RISCVISD::BCOMPRESSW
-                         : RISCVISD::BDECOMPRESSW;
-      SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
-      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
-      break;
-    }
-    case Intrinsic::riscv_bfp: {
-      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
-             "Unexpected custom legalisation");
-      SDValue NewOp1 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue NewOp2 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
-      SDValue Res = DAG.getNode(RISCVISD::BFPW, DL, MVT::i64, NewOp1, NewOp2);
-      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
-      break;
-    }
     case Intrinsic::riscv_vmv_x_s: {
       EVT VT = N->getValueType(0);
       MVT XLenVT = Subtarget.getXLenVT();
@@ -6325,8 +6285,25 @@
           DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi));
       break;
     }
-    }
+#define CASE_EXTEND_TWO_OPERANDS(intrinsic, opcode)                             \
+  case Intrinsic::intrinsic: {                                                 \
+    assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&            \
+           "Unexpected custom legalisation");                                  \
+    SDValue NewOp1 =                                                           \
+        DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));          \
+    SDValue NewOp2 =                                                           \
+        DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));          \
+    SDValue Res = DAG.getNode(RISCVISD::opcode, DL, MVT::i64, NewOp1, NewOp2); \
+    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));          \
     break;
+    }
+    CASE_EXTEND_TWO_OPERANDS(riscv_grev, GREVW)
+    CASE_EXTEND_TWO_OPERANDS(riscv_gorc, GORCW)
+    CASE_EXTEND_TWO_OPERANDS(riscv_bcompress, BCOMPRESSW)
+    CASE_EXTEND_TWO_OPERANDS(riscv_bdecompress, BDECOMPRESSW)
+    CASE_EXTEND_TWO_OPERANDS(riscv_bfp, BFPW)
+#undef CASE_EXTEND_TWO_OPERANDS
+  } break;
   }
   case ISD::VECREDUCE_ADD:
   case ISD::VECREDUCE_AND:


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