[PATCH] D114652: [AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range

Venkata Ramanaiah Nalamothu via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 14 11:22:52 PST 2022 

RamNalamothu updated this revision to Diff 400091.
RamNalamothu added a comment.
Herald added a subscriber: MatzeB.

Fixed an issue exposed by OpenMP LIT test failures.

determineCalleeSavesSGPR() now explicitly adds S30 and S31 to CSR list
when we have calls and this is needed for cases like D117243 <https://reviews.llvm.org/D117243>.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114652/new/

https://reviews.llvm.org/D114652

Files:
  llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
  llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
  llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmax.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
  llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
  llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
  llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
  llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
  llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
  llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
  llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
  llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
  llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
  llvm/test/CodeGen/AMDGPU/fpow.ll
  llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/fshr.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
  llvm/test/CodeGen/AMDGPU/indirect-call.ll
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
  llvm/test/CodeGen/AMDGPU/ipra.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
  llvm/test/CodeGen/AMDGPU/llvm.powi.ll
  llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
  llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/nested-calls.ll
  llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
  llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
  llvm/test/CodeGen/AMDGPU/save-fp.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
  llvm/test/CodeGen/AMDGPU/sibling-call.ll
  llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
  llvm/test/CodeGen/AMDGPU/stack-realign.ll
  llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
  llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
  llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
  llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
  llvm/test/CodeGen/AMDGPU/udiv.ll
  llvm/test/CodeGen/AMDGPU/udiv64.ll
  llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
  llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/AMDGPU/urem64.ll
  llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
  llvm/test/CodeGen/AMDGPU/wave32.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
  llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
  llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir

More information about the llvm-commits mailing list