[PATCH] D117310: [RISCV] Add CSRs defined in the recently ratified Smstateen extension

[Alex Bradbury via Phabricator via llvm-commits]

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The "RISC-V State Enable Extension" was ratified at the end of at the
end of last year though hasn't yet been integrated in the main
specification documents (see
https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions).

This commit adds the CSRs defined by this extension in
https://github.com/riscv/riscv-state-enable/releases/download/v0.6.3/Smstateen.pdf.

Note I've defined the CSRs together in a single foreach loop. This is easiest to read when compared to the Smstateen spec. If/when these CSRs are merged into the tables in the privileged spec, we may want to loop back to match however they are grouped there.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117310

Files:
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/MC/RISCV/hypervisor-csr-names.s
  llvm/test/MC/RISCV/machine-csr-names.s
  llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
  llvm/test/MC/RISCV/rv32-machine-csr-names.s
  llvm/test/MC/RISCV/rv32-only-csr-names.s
  llvm/test/MC/RISCV/supervisor-csr-names.s

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