[llvm] 4a4a652 - [RISCV][NFC] Use TableGen 'foreach' to simplify repetitive CSR definitions
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 14 03:59:50 PST 2022
Author: Alex Bradbury
Date: 2022-01-14T11:59:39Z
New Revision: 4a4a652f34d00120867757fd19aac3c8d85d9451
URL: https://github.com/llvm/llvm-project/commit/4a4a652f34d00120867757fd19aac3c8d85d9451
DIFF: https://github.com/llvm/llvm-project/commit/4a4a652f34d00120867757fd19aac3c8d85d9451.diff
LOG: [RISCV][NFC] Use TableGen 'foreach' to simplify repetitive CSR definitions
Make the definitions of hpmcounter3-hpmcounter31,
hpmcounter3h-hpmcounter31h, mhpmcounter3-mhpmcounter31,
mhpmcounter3h-mhpmcounter31h, pmpaddr0-pmpaddr63, mhpmevent3-31, and
pmpcfg0-15 substantially less repetitive using a foreach loop.
Differential Revision: https://reviews.llvm.org/D117227
Added:
Modified:
llvm/lib/Target/RISCV/RISCVSystemOperands.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 3206a3a30142d..2a93036f54e49 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -102,70 +102,18 @@ def CYCLE : SysReg<"cycle", 0xC00>;
def TIME : SysReg<"time", 0xC01>;
def INSTRET : SysReg<"instret", 0xC02>;
-def : SysReg<"hpmcounter3", 0xC03>;
-def : SysReg<"hpmcounter4", 0xC04>;
-def : SysReg<"hpmcounter5", 0xC05>;
-def : SysReg<"hpmcounter6", 0xC06>;
-def : SysReg<"hpmcounter7", 0xC07>;
-def : SysReg<"hpmcounter8", 0xC08>;
-def : SysReg<"hpmcounter9", 0xC09>;
-def : SysReg<"hpmcounter10", 0xC0A>;
-def : SysReg<"hpmcounter11", 0xC0B>;
-def : SysReg<"hpmcounter12", 0xC0C>;
-def : SysReg<"hpmcounter13", 0xC0D>;
-def : SysReg<"hpmcounter14", 0xC0E>;
-def : SysReg<"hpmcounter15", 0xC0F>;
-def : SysReg<"hpmcounter16", 0xC10>;
-def : SysReg<"hpmcounter17", 0xC11>;
-def : SysReg<"hpmcounter18", 0xC12>;
-def : SysReg<"hpmcounter19", 0xC13>;
-def : SysReg<"hpmcounter20", 0xC14>;
-def : SysReg<"hpmcounter21", 0xC15>;
-def : SysReg<"hpmcounter22", 0xC16>;
-def : SysReg<"hpmcounter23", 0xC17>;
-def : SysReg<"hpmcounter24", 0xC18>;
-def : SysReg<"hpmcounter25", 0xC19>;
-def : SysReg<"hpmcounter26", 0xC1A>;
-def : SysReg<"hpmcounter27", 0xC1B>;
-def : SysReg<"hpmcounter28", 0xC1C>;
-def : SysReg<"hpmcounter29", 0xC1D>;
-def : SysReg<"hpmcounter30", 0xC1E>;
-def : SysReg<"hpmcounter31", 0xC1F>;
+// hpmcounter3-hpmcounter31 at 0xC03-0xC1F.
+foreach i = 3...31 in
+ def : SysReg<"hpmcounter"#i, !add(0xC03, !sub(i, 3))>;
let isRV32Only = 1 in {
def CYCLEH : SysReg<"cycleh", 0xC80>;
def TIMEH : SysReg<"timeh", 0xC81>;
def INSTRETH : SysReg<"instreth", 0xC82>;
-def: SysReg<"hpmcounter3h", 0xC83>;
-def: SysReg<"hpmcounter4h", 0xC84>;
-def: SysReg<"hpmcounter5h", 0xC85>;
-def: SysReg<"hpmcounter6h", 0xC86>;
-def: SysReg<"hpmcounter7h", 0xC87>;
-def: SysReg<"hpmcounter8h", 0xC88>;
-def: SysReg<"hpmcounter9h", 0xC89>;
-def: SysReg<"hpmcounter10h", 0xC8A>;
-def: SysReg<"hpmcounter11h", 0xC8B>;
-def: SysReg<"hpmcounter12h", 0xC8C>;
-def: SysReg<"hpmcounter13h", 0xC8D>;
-def: SysReg<"hpmcounter14h", 0xC8E>;
-def: SysReg<"hpmcounter15h", 0xC8F>;
-def: SysReg<"hpmcounter16h", 0xC90>;
-def: SysReg<"hpmcounter17h", 0xC91>;
-def: SysReg<"hpmcounter18h", 0xC92>;
-def: SysReg<"hpmcounter19h", 0xC93>;
-def: SysReg<"hpmcounter20h", 0xC94>;
-def: SysReg<"hpmcounter21h", 0xC95>;
-def: SysReg<"hpmcounter22h", 0xC96>;
-def: SysReg<"hpmcounter23h", 0xC97>;
-def: SysReg<"hpmcounter24h", 0xC98>;
-def: SysReg<"hpmcounter25h", 0xC99>;
-def: SysReg<"hpmcounter26h", 0xC9A>;
-def: SysReg<"hpmcounter27h", 0xC9B>;
-def: SysReg<"hpmcounter28h", 0xC9C>;
-def: SysReg<"hpmcounter29h", 0xC9D>;
-def: SysReg<"hpmcounter30h", 0xC9E>;
-def: SysReg<"hpmcounter31h", 0xC9F>;
+// hpmcounter3h-hpmcounter31h at 0xC83-0xC9F.
+foreach i = 3...31 in
+ def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>;
}
//===----------------------------------------------------------------------===//
@@ -318,96 +266,16 @@ def : SysReg<"mseccfgh", 0x757>;
//===----------------------------------------------------------------------===//
// Machine Protection and Translation
//===----------------------------------------------------------------------===//
-def : SysReg<"pmpcfg0", 0x3A0>;
-let isRV32Only = 1 in
-def : SysReg<"pmpcfg1", 0x3A1>;
-def : SysReg<"pmpcfg2", 0x3A2>;
-let isRV32Only = 1 in
-def : SysReg<"pmpcfg3", 0x3A3>;
-def : SysReg<"pmpcfg4", 0x3A4>;
-let isRV32Only = 1 in
-def : SysReg<"pmpcfg5", 0x3A5>;
-def : SysReg<"pmpcfg6", 0x3A6>;
-let isRV32Only = 1 in
-def : SysReg<"pmpcfg7", 0x3A7>;
-def : SysReg<"pmpcfg8", 0x3A8>;
-let isRV32Only = 1 in
-def : SysReg<"pmpcfg9", 0x3A9>;
-def : SysReg<"pmpcfg10", 0x3AA>;
-let isRV32Only = 1 in
-def : SysReg<"pmpcfg11", 0x3AB>;
-def : SysReg<"pmpcfg12", 0x3AC>;
-let isRV32Only = 1 in
-def : SysReg<"pmpcfg13", 0x3AD>;
-def : SysReg<"pmpcfg14", 0x3AE>;
-let isRV32Only = 1 in
-def : SysReg<"pmpcfg15", 0x3AF>;
-
-def : SysReg<"pmpaddr0", 0x3B0>;
-def : SysReg<"pmpaddr1", 0x3B1>;
-def : SysReg<"pmpaddr2", 0x3B2>;
-def : SysReg<"pmpaddr3", 0x3B3>;
-def : SysReg<"pmpaddr4", 0x3B4>;
-def : SysReg<"pmpaddr5", 0x3B5>;
-def : SysReg<"pmpaddr6", 0x3B6>;
-def : SysReg<"pmpaddr7", 0x3B7>;
-def : SysReg<"pmpaddr8", 0x3B8>;
-def : SysReg<"pmpaddr9", 0x3B9>;
-def : SysReg<"pmpaddr10", 0x3BA>;
-def : SysReg<"pmpaddr11", 0x3BB>;
-def : SysReg<"pmpaddr12", 0x3BC>;
-def : SysReg<"pmpaddr13", 0x3BD>;
-def : SysReg<"pmpaddr14", 0x3BE>;
-def : SysReg<"pmpaddr15", 0x3BF>;
-def : SysReg<"pmpaddr16", 0x3C0>;
-def : SysReg<"pmpaddr17", 0x3C1>;
-def : SysReg<"pmpaddr18", 0x3C2>;
-def : SysReg<"pmpaddr19", 0x3C3>;
-def : SysReg<"pmpaddr20", 0x3C4>;
-def : SysReg<"pmpaddr21", 0x3C5>;
-def : SysReg<"pmpaddr22", 0x3C6>;
-def : SysReg<"pmpaddr23", 0x3C7>;
-def : SysReg<"pmpaddr24", 0x3C8>;
-def : SysReg<"pmpaddr25", 0x3C9>;
-def : SysReg<"pmpaddr26", 0x3CA>;
-def : SysReg<"pmpaddr27", 0x3CB>;
-def : SysReg<"pmpaddr28", 0x3CC>;
-def : SysReg<"pmpaddr29", 0x3CD>;
-def : SysReg<"pmpaddr30", 0x3CE>;
-def : SysReg<"pmpaddr31", 0x3CF>;
-def : SysReg<"pmpaddr32", 0x3D0>;
-def : SysReg<"pmpaddr33", 0x3D1>;
-def : SysReg<"pmpaddr34", 0x3D2>;
-def : SysReg<"pmpaddr35", 0x3D3>;
-def : SysReg<"pmpaddr36", 0x3D4>;
-def : SysReg<"pmpaddr37", 0x3D5>;
-def : SysReg<"pmpaddr38", 0x3D6>;
-def : SysReg<"pmpaddr39", 0x3D7>;
-def : SysReg<"pmpaddr40", 0x3D8>;
-def : SysReg<"pmpaddr41", 0x3D9>;
-def : SysReg<"pmpaddr42", 0x3DA>;
-def : SysReg<"pmpaddr43", 0x3DB>;
-def : SysReg<"pmpaddr44", 0x3DC>;
-def : SysReg<"pmpaddr45", 0x3DD>;
-def : SysReg<"pmpaddr46", 0x3DE>;
-def : SysReg<"pmpaddr47", 0x3DF>;
-def : SysReg<"pmpaddr48", 0x3E0>;
-def : SysReg<"pmpaddr49", 0x3E1>;
-def : SysReg<"pmpaddr50", 0x3E2>;
-def : SysReg<"pmpaddr51", 0x3E3>;
-def : SysReg<"pmpaddr52", 0x3E4>;
-def : SysReg<"pmpaddr53", 0x3E5>;
-def : SysReg<"pmpaddr54", 0x3E6>;
-def : SysReg<"pmpaddr55", 0x3E7>;
-def : SysReg<"pmpaddr56", 0x3E8>;
-def : SysReg<"pmpaddr57", 0x3E9>;
-def : SysReg<"pmpaddr58", 0x3EA>;
-def : SysReg<"pmpaddr59", 0x3EB>;
-def : SysReg<"pmpaddr60", 0x3EC>;
-def : SysReg<"pmpaddr61", 0x3ED>;
-def : SysReg<"pmpaddr62", 0x3EE>;
-def : SysReg<"pmpaddr63", 0x3EF>;
+// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only.
+foreach i = 0...15 in {
+ let isRV32Only = !and(i, 1) in
+ def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>;
+}
+
+// pmpaddr0-pmpaddr63 at 0x3B0-0x3EF.
+foreach i = 0...63 in
+ def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
//===----------------------------------------------------------------------===//
// Machine Counter and Timers
@@ -415,69 +283,17 @@ def : SysReg<"pmpaddr63", 0x3EF>;
def : SysReg<"mcycle", 0xB00>;
def : SysReg<"minstret", 0xB02>;
-def : SysReg<"mhpmcounter3", 0xB03>;
-def : SysReg<"mhpmcounter4", 0xB04>;
-def : SysReg<"mhpmcounter5", 0xB05>;
-def : SysReg<"mhpmcounter6", 0xB06>;
-def : SysReg<"mhpmcounter7", 0xB07>;
-def : SysReg<"mhpmcounter8", 0xB08>;
-def : SysReg<"mhpmcounter9", 0xB09>;
-def : SysReg<"mhpmcounter10", 0xB0A>;
-def : SysReg<"mhpmcounter11", 0xB0B>;
-def : SysReg<"mhpmcounter12", 0xB0C>;
-def : SysReg<"mhpmcounter13", 0xB0D>;
-def : SysReg<"mhpmcounter14", 0xB0E>;
-def : SysReg<"mhpmcounter15", 0xB0F>;
-def : SysReg<"mhpmcounter16", 0xB10>;
-def : SysReg<"mhpmcounter17", 0xB11>;
-def : SysReg<"mhpmcounter18", 0xB12>;
-def : SysReg<"mhpmcounter19", 0xB13>;
-def : SysReg<"mhpmcounter20", 0xB14>;
-def : SysReg<"mhpmcounter21", 0xB15>;
-def : SysReg<"mhpmcounter22", 0xB16>;
-def : SysReg<"mhpmcounter23", 0xB17>;
-def : SysReg<"mhpmcounter24", 0xB18>;
-def : SysReg<"mhpmcounter25", 0xB19>;
-def : SysReg<"mhpmcounter26", 0xB1A>;
-def : SysReg<"mhpmcounter27", 0xB1B>;
-def : SysReg<"mhpmcounter28", 0xB1C>;
-def : SysReg<"mhpmcounter29", 0xB1D>;
-def : SysReg<"mhpmcounter30", 0xB1E>;
-def : SysReg<"mhpmcounter31", 0xB1F>;
+// mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F.
+foreach i = 3...31 in
+ def : SysReg<"mhpmcounter"#i, !add(0xB03, !sub(i, 3))>;
let isRV32Only = 1 in {
def: SysReg<"mcycleh", 0xB80>;
def: SysReg<"minstreth", 0xB82>;
-def: SysReg<"mhpmcounter3h", 0xB83>;
-def: SysReg<"mhpmcounter4h", 0xB84>;
-def: SysReg<"mhpmcounter5h", 0xB85>;
-def: SysReg<"mhpmcounter6h", 0xB86>;
-def: SysReg<"mhpmcounter7h", 0xB87>;
-def: SysReg<"mhpmcounter8h", 0xB88>;
-def: SysReg<"mhpmcounter9h", 0xB89>;
-def: SysReg<"mhpmcounter10h", 0xB8A>;
-def: SysReg<"mhpmcounter11h", 0xB8B>;
-def: SysReg<"mhpmcounter12h", 0xB8C>;
-def: SysReg<"mhpmcounter13h", 0xB8D>;
-def: SysReg<"mhpmcounter14h", 0xB8E>;
-def: SysReg<"mhpmcounter15h", 0xB8F>;
-def: SysReg<"mhpmcounter16h", 0xB90>;
-def: SysReg<"mhpmcounter17h", 0xB91>;
-def: SysReg<"mhpmcounter18h", 0xB92>;
-def: SysReg<"mhpmcounter19h", 0xB93>;
-def: SysReg<"mhpmcounter20h", 0xB94>;
-def: SysReg<"mhpmcounter21h", 0xB95>;
-def: SysReg<"mhpmcounter22h", 0xB96>;
-def: SysReg<"mhpmcounter23h", 0xB97>;
-def: SysReg<"mhpmcounter24h", 0xB98>;
-def: SysReg<"mhpmcounter25h", 0xB99>;
-def: SysReg<"mhpmcounter26h", 0xB9A>;
-def: SysReg<"mhpmcounter27h", 0xB9B>;
-def: SysReg<"mhpmcounter28h", 0xB9C>;
-def: SysReg<"mhpmcounter29h", 0xB9D>;
-def: SysReg<"mhpmcounter30h", 0xB9E>;
-def: SysReg<"mhpmcounter31h", 0xB9F>;
+// mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F.
+foreach i = 3...31 in
+ def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>;
}
//===----------------------------------------------------------------------===//
@@ -486,35 +302,9 @@ def: SysReg<"mhpmcounter31h", 0xB9F>;
let AltName = "mucounteren" in // Privileged spec v1.9.1 Name
def : SysReg<"mcountinhibit", 0x320>;
-def : SysReg<"mhpmevent3", 0x323>;
-def : SysReg<"mhpmevent4", 0x324>;
-def : SysReg<"mhpmevent5", 0x325>;
-def : SysReg<"mhpmevent6", 0x326>;
-def : SysReg<"mhpmevent7", 0x327>;
-def : SysReg<"mhpmevent8", 0x328>;
-def : SysReg<"mhpmevent9", 0x329>;
-def : SysReg<"mhpmevent10", 0x32A>;
-def : SysReg<"mhpmevent11", 0x32B>;
-def : SysReg<"mhpmevent12", 0x32C>;
-def : SysReg<"mhpmevent13", 0x32D>;
-def : SysReg<"mhpmevent14", 0x32E>;
-def : SysReg<"mhpmevent15", 0x32F>;
-def : SysReg<"mhpmevent16", 0x330>;
-def : SysReg<"mhpmevent17", 0x331>;
-def : SysReg<"mhpmevent18", 0x332>;
-def : SysReg<"mhpmevent19", 0x333>;
-def : SysReg<"mhpmevent20", 0x334>;
-def : SysReg<"mhpmevent21", 0x335>;
-def : SysReg<"mhpmevent22", 0x336>;
-def : SysReg<"mhpmevent23", 0x337>;
-def : SysReg<"mhpmevent24", 0x338>;
-def : SysReg<"mhpmevent25", 0x339>;
-def : SysReg<"mhpmevent26", 0x33A>;
-def : SysReg<"mhpmevent27", 0x33B>;
-def : SysReg<"mhpmevent28", 0x33C>;
-def : SysReg<"mhpmevent29", 0x33D>;
-def : SysReg<"mhpmevent30", 0x33E>;
-def : SysReg<"mhpmevent31", 0x33F>;
+// mhpmevent3-mhpmevent31 at 0x323-0x33F.
+foreach i = 3...31 in
+ def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>;
//===----------------------------------------------------------------------===//
// Debug/ Trace Registers (shared with Debug Mode)
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