[PATCH] D117290: [RISCV] Add scheduler for bfp instruction in Zbf extension

[WangLian via Phabricator via llvm-commits]

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Try to add scheduler for bfp instruction in Zbf extension


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117290

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSchedRocket.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleB.td


Index: llvm/lib/Target/RISCV/RISCVScheduleB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVScheduleB.td
+++ llvm/lib/Target/RISCV/RISCVScheduleB.td
@@ -26,6 +26,10 @@
 def WriteREV8        : SchedWrite;
 def WriteORCB        : SchedWrite;
 
+// Zbf extension
+def WriteBFP         : SchedWrite; // BFP
+def WriteBFP32       : SchedWrite; // BFPW
+
 /// Define scheduler resources associated with use operands.
 
 // Zba extension
@@ -46,6 +50,10 @@
 def ReadREV8        : SchedRead;
 def ReadORCB        : SchedRead;
 
+// Zbf extension
+def ReadBFP      : SchedRead; // BFP
+def ReadBFP32    : SchedRead; // BFPW
+
 /// Define default scheduler resources for B.
 
 multiclass UnsupportedSchedZba {
@@ -87,3 +95,13 @@
 def : ReadAdvance<ReadORCB, 0>;
 }
 }
+
+multiclass UnsupportedSchedZbf {
+let Unsupported = true in {
+def : WriteRes<WriteBFP, []>;
+def : WriteRes<WriteBFP32, []>;
+
+def : ReadAdvance<ReadBFP, 0>;
+def : ReadAdvance<ReadBFP32, 0>;
+}
+}
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -224,5 +224,6 @@
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
+defm : UnsupportedSchedZbf;
 defm : UnsupportedSchedZfh;
 }
Index: llvm/lib/Target/RISCV/RISCVSchedRocket.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -237,5 +237,6 @@
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
+defm : UnsupportedSchedZbf;
 defm : UnsupportedSchedZfh;
 }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -472,7 +472,7 @@
 } // Predicates = [HasStdExtZbm, IsRV64]
 
 let Predicates = [HasStdExtZbf] in
-def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
+def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[WriteBFP, ReadBFP, ReadBFP]>;
 
 let Predicates = [HasStdExtZbp] in {
 def SHFLI   : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
@@ -553,7 +553,7 @@
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbf, IsRV64] in
-def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>;
+def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[WriteBFP32, ReadBFP32, ReadBFP32]>;
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in


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