[llvm] 3174525 - [RISCV] Add inline asm f32 test cases with D extension. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-01-13T21:52:46-08:00
New Revision: 317452551683cb4703c0b2af84e41044c9b24f56

URL: https://github.com/llvm/llvm-project/commit/317452551683cb4703c0b2af84e41044c9b24f56
DIFF: https://github.com/llvm/llvm-project/commit/317452551683cb4703c0b2af84e41044c9b24f56.diff

LOG: [RISCV] Add inline asm f32 test cases with D extension. NFC

Using named registers as input or output constraints creates fcvt.d.s
and fcvt.s.d instructions around the inline assembly.

This makes the data unusable by the inline assembly and corrupts
the results of the inline assembly.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
index 25bce62952aed..0055480eb2c99 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
@@ -3,10 +3,35 @@
 ; RUN:   | FileCheck -check-prefix=RV32F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64F %s
+; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32D %s
+; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64D %s
 
 @gf = external global float
 
 define float @constraint_f_float(float %a) nounwind {
+; RV32-LABEL: constraint_f_float:
+; RV32:       # %bb.0:
+; RV32-NEXT:    lui a1, %hi(gf)
+; RV32-NEXT:    flw ft0, %lo(gf)(a1)
+; RV32-NEXT:    fmv.w.x ft1, a0
+; RV32-NEXT:    #APP
+; RV32-NEXT:    fadd.s ft0, ft1, ft0
+; RV32-NEXT:    #NO_APP
+; RV32-NEXT:    fmv.x.w a0, ft0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: constraint_f_float:
+; RV64:       # %bb.0:
+; RV64-NEXT:    lui a1, %hi(gf)
+; RV64-NEXT:    flw ft0, %lo(gf)(a1)
+; RV64-NEXT:    fmv.w.x ft1, a0
+; RV64-NEXT:    #APP
+; RV64-NEXT:    fadd.s ft0, ft1, ft0
+; RV64-NEXT:    #NO_APP
+; RV64-NEXT:    fmv.x.w a0, ft0
+; RV64-NEXT:    ret
 ; RV32F-LABEL: constraint_f_float:
 ; RV32F:       # %bb.0:
 ; RV32F-NEXT:    lui a1, %hi(gf)
@@ -28,6 +53,28 @@ define float @constraint_f_float(float %a) nounwind {
 ; RV64F-NEXT:    #NO_APP
 ; RV64F-NEXT:    fmv.x.w a0, ft0
 ; RV64F-NEXT:    ret
+;
+; RV32D-LABEL: constraint_f_float:
+; RV32D:       # %bb.0:
+; RV32D-NEXT:    lui a1, %hi(gf)
+; RV32D-NEXT:    flw ft0, %lo(gf)(a1)
+; RV32D-NEXT:    fmv.w.x ft1, a0
+; RV32D-NEXT:    #APP
+; RV32D-NEXT:    fadd.s ft0, ft1, ft0
+; RV32D-NEXT:    #NO_APP
+; RV32D-NEXT:    fmv.x.w a0, ft0
+; RV32D-NEXT:    ret
+;
+; RV64D-LABEL: constraint_f_float:
+; RV64D:       # %bb.0:
+; RV64D-NEXT:    lui a1, %hi(gf)
+; RV64D-NEXT:    flw ft0, %lo(gf)(a1)
+; RV64D-NEXT:    fmv.w.x ft1, a0
+; RV64D-NEXT:    #APP
+; RV64D-NEXT:    fadd.s ft0, ft1, ft0
+; RV64D-NEXT:    #NO_APP
+; RV64D-NEXT:    fmv.x.w a0, ft0
+; RV64D-NEXT:    ret
   %1 = load float, float* @gf
   %2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1)
   ret float %2
@@ -55,6 +102,34 @@ define float @constraint_f_float_abi_name(float %a) nounwind {
 ; RV64F-NEXT:    #NO_APP
 ; RV64F-NEXT:    fmv.x.w a0, ft0
 ; RV64F-NEXT:    ret
+;
+; RV32D-LABEL: constraint_f_float_abi_name:
+; RV32D:       # %bb.0:
+; RV32D-NEXT:    lui a1, %hi(gf)
+; RV32D-NEXT:    flw ft0, %lo(gf)(a1)
+; RV32D-NEXT:    fmv.w.x ft1, a0
+; RV32D-NEXT:    fcvt.d.s fa0, ft1
+; RV32D-NEXT:    fcvt.d.s fs0, ft0
+; RV32D-NEXT:    #APP
+; RV32D-NEXT:    fadd.s ft0, fa0, fs0
+; RV32D-NEXT:    #NO_APP
+; RV32D-NEXT:    fcvt.s.d ft0, ft0
+; RV32D-NEXT:    fmv.x.w a0, ft0
+; RV32D-NEXT:    ret
+;
+; RV64D-LABEL: constraint_f_float_abi_name:
+; RV64D:       # %bb.0:
+; RV64D-NEXT:    lui a1, %hi(gf)
+; RV64D-NEXT:    flw ft0, %lo(gf)(a1)
+; RV64D-NEXT:    fmv.w.x ft1, a0
+; RV64D-NEXT:    fcvt.d.s fa0, ft1
+; RV64D-NEXT:    fcvt.d.s fs0, ft0
+; RV64D-NEXT:    #APP
+; RV64D-NEXT:    fadd.s ft0, fa0, fs0
+; RV64D-NEXT:    #NO_APP
+; RV64D-NEXT:    fcvt.s.d ft0, ft0
+; RV64D-NEXT:    fmv.x.w a0, ft0
+; RV64D-NEXT:    ret
   %1 = load float, float* @gf
   %2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1)
   ret float %2