[PATCH] D117269: [RISCV] Optimize some special mul operation in Zba extension

WangLian via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jan 13 18:35:39 PST 2022


Jimerlife created this revision.
Jimerlife added reviewers: craig.topper, asb, benshi001, luismarques.
Jimerlife added a project: LLVM.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Jimerlife requested review of this revision.
Herald added subscribers: llvm-commits, jacquesguan, MaskRay.

Optimized (mul x, 27), (mul x, 45), (mul x, 81) in previous patterns may has some problem. Cannot generate two same assembly SH3ADD x, x after isel, so I removed those groups patterns and add some mul optimization which referred to before optimization.

Before:
(mul x, 27) -> (SH1ADD (SH3ADD x, x), (SH3ADD x, x))
(mul x, 45) -> (SH2ADD (SH3ADD x, x), (SH3ADD x, x))
(mul x, 81) -> (SH3ADD (SH3ADD x, x), (SH3ADD x, x))

My Add:
(mul x, 23) -> (SH2ADD (SH2ADD x, x), (SH1ADD x, x))
(mul x, 43) -> (SH3ADD (SH2ADD x, x), (SH1ADD x, x))
(mul x, 39) -> (SH2ADD (SH3ADD x, x), (SH1ADD x, x))
(mul x, 75) -> (SH3ADD (SH3ADD x, x), (SH1ADD x, x))
(mul x, 77) -> (SH3ADD (SH3ADD x, x), (SH2ADD x, x))


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117269

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv64zba.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D117269.399862.patch
Type: text/x-patch
Size: 4152 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220114/d62f1728/attachment.bin>


More information about the llvm-commits mailing list