[PATCH] D117227: [RISCV][NFC] Use TableGen 'foreach' to simplify repetitive CSR definitions

[Shao-Ce SUN via Phabricator via llvm-commits]

achieveartificialintelligence added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSystemOperands.td:269-292
 def : SysReg<"pmpcfg0", 0x3A0>;
 let isRV32Only = 1 in
 def : SysReg<"pmpcfg1", 0x3A1>;
 def : SysReg<"pmpcfg2", 0x3A2>;
 let isRV32Only = 1 in
 def : SysReg<"pmpcfg3", 0x3A3>;
 def : SysReg<"pmpcfg4", 0x3A4>;
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achieveartificialintelligence wrote:
> asb wrote:
> > achieveartificialintelligence wrote:
> > > I think `pmpcfg` can also be compressed.
> > It could, but I wasn't convinced it would be an improvement given the interleaving of the RV32-only odd registers along with the RV32/RV64 even registers.
> // pmpcfg0-pmpcfg15 at 0x3A0-0x3AF.
> foreach i = 0...15 in
>   let isRV32Only = !and(i, 1) in
>   def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>;
> ```// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF.
> foreach i = 0...15 in
>   let isRV32Only = !and(i, 1) in
>   def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>;```

How about this way?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117227/new/

https://reviews.llvm.org/D117227