[llvm] 0c6c588 - [DAG] Add ISD::ROTL/ROTR to TargetLoweringBase::isBinOp
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 13 06:33:05 PST 2022
Author: Simon Pilgrim
Date: 2022-01-13T14:32:14Z
New Revision: 0c6c588a9b9cd17c8eaa95b7ad8678bae1d7f057
URL: https://github.com/llvm/llvm-project/commit/0c6c588a9b9cd17c8eaa95b7ad8678bae1d7f057
DIFF: https://github.com/llvm/llvm-project/commit/0c6c588a9b9cd17c8eaa95b7ad8678bae1d7f057.diff
LOG: [DAG] Add ISD::ROTL/ROTR to TargetLoweringBase::isBinOp
Allows shuffle combining through rotation nodes
Added:
Modified:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/test/CodeGen/X86/combine-rotates.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index e9b2df85e7f57..3d67f0c0ca296 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2526,6 +2526,8 @@ class TargetLoweringBase {
case ISD::SHL:
case ISD::SRL:
case ISD::SRA:
+ case ISD::ROTL:
+ case ISD::ROTR:
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
diff --git a/llvm/test/CodeGen/X86/combine-rotates.ll b/llvm/test/CodeGen/X86/combine-rotates.ll
index 22e6332fdc117..ed9581d71177e 100644
--- a/llvm/test/CodeGen/X86/combine-rotates.ll
+++ b/llvm/test/CodeGen/X86/combine-rotates.ll
@@ -339,37 +339,30 @@ define <4 x i32> @rotate_demanded_bits_3(<4 x i32>, <4 x i32>) {
define <4 x i32> @rotl_binop_shuffle(<4 x i32>, <4 x i32>) {
; SSE2-LABEL: rotl_binop_shuffle:
; SSE2: # %bb.0:
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,2,1,0]
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pslld $23, %xmm1
; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
-; SSE2-NEXT: pmuludq %xmm0, %xmm3
-; SSE2-NEXT: pmuludq %xmm1, %xmm2
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,1,2,3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[3,1,2,3]
-; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,0,2,3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,0,2,3]
-; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; SSE2-NEXT: por %xmm1, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE2-NEXT: pmuludq %xmm1, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE2-NEXT: pmuludq %xmm2, %xmm1
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq
;
; XOP-LABEL: rotl_binop_shuffle:
; XOP: # %bb.0:
-; XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
-; XOP-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
-; XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; XOP-NEXT: retq
;
; AVX2-LABEL: rotl_binop_shuffle:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
-; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm2
@@ -377,15 +370,11 @@ define <4 x i32> @rotl_binop_shuffle(<4 x i32>, <4 x i32>) {
; AVX2-NEXT: vpsubd %xmm1, %xmm3, %xmm1
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpor %xmm0, %xmm2, %xmm0
-; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; AVX2-NEXT: retq
;
; AVX512-LABEL: rotl_binop_shuffle:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
-; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
; AVX512-NEXT: vprolvd %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; AVX512-NEXT: retq
%3 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%4 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
@@ -397,40 +386,36 @@ define <4 x i32> @rotl_binop_shuffle(<4 x i32>, <4 x i32>) {
define <4 x i32> @rotr_binop_shuffle(<4 x i32>, <4 x i32>) {
; SSE2-LABEL: rotr_binop_shuffle:
; SSE2: # %bb.0:
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,2,2]
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,2,3,3]
; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: andl $31, %eax
; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psllq %xmm1, %xmm2
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,0,0]
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2-NEXT: psllq %xmm1, %xmm0
-; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm2[3,1]
+; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm2[1,3]
; SSE2-NEXT: retq
;
; XOP-LABEL: rotr_binop_shuffle:
; XOP: # %bb.0:
-; XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; XOP-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
-; XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; XOP-NEXT: retq
;
; AVX2-LABEL: rotr_binop_shuffle:
; AVX2: # %bb.0:
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[3,3,2,2]
+; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,2,3,3]
; AVX2-NEXT: vpsllq %xmm1, %xmm2, %xmm2
-; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,0,0]
+; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; AVX2-NEXT: vpsllq %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,1],xmm2[3,1]
+; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm2[1,3]
; AVX2-NEXT: retq
;
; AVX512-LABEL: rotr_binop_shuffle:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; AVX512-NEXT: vpbroadcastd %xmm1, %xmm1
; AVX512-NEXT: vprolvd %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
; AVX512-NEXT: retq
%3 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%4 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer
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