[PATCH] D117219: [LSV] Vectorize loads of vectors by turning it into a larger vector

[Benjamin Kramer via Phabricator via llvm-commits]

bkramer created this revision.
bkramer added reviewers: arsenm, tra.
Herald added subscribers: asavonic, kerbowa, hiraditya, tpr, nhaehnle, jvesely, jholewinski.
bkramer requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Use shufflevector to do the subvector extracts. This allows a lot more
load merging on AMDGPU and also on NVPTX when <2 x half> is involved.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117219

Files:
  llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/ashr.v2i16.ll
  llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
  llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
  llvm/test/CodeGen/AMDGPU/fshl.ll
  llvm/test/CodeGen/AMDGPU/fshr.ll
  llvm/test/CodeGen/AMDGPU/half.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
  llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
  llvm/test/CodeGen/AMDGPU/memory_clause.ll
  llvm/test/CodeGen/AMDGPU/min.ll
  llvm/test/CodeGen/AMDGPU/mul_int24.ll
  llvm/test/CodeGen/AMDGPU/sdiv.ll
  llvm/test/CodeGen/AMDGPU/sdiv64.ll
  llvm/test/CodeGen/AMDGPU/select-vectors.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll
  llvm/test/CodeGen/AMDGPU/shl.ll
  llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
  llvm/test/CodeGen/AMDGPU/sra.ll
  llvm/test/CodeGen/AMDGPU/srl.ll
  llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
  llvm/test/CodeGen/AMDGPU/udiv.ll
  llvm/test/CodeGen/AMDGPU/urem64.ll
  llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll

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