[llvm] 821dd3b - [FileCheck] Allow literal '['s before "[[var...]]"
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 13 01:52:38 PST 2022
Author: Jay Foad
Date: 2022-01-13T09:47:37Z
New Revision: 821dd3b0e5b7811857e0fd0d1e9fca5ae2546cb4
URL: https://github.com/llvm/llvm-project/commit/821dd3b0e5b7811857e0fd0d1e9fca5ae2546cb4
DIFF: https://github.com/llvm/llvm-project/commit/821dd3b0e5b7811857e0fd0d1e9fca5ae2546cb4.diff
LOG: [FileCheck] Allow literal '['s before "[[var...]]"
Change FileCheck to accept patterns like "[[[var...]]" and treat the
excess open brackets at the start as literals.
This makes the patterns for matching assembler output with literal
brackets much cleaner. For example an AMDGPU pattern that used to be
written like:
buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
can now be:
buffer_store_dwordx2 v[[[LO]]:[[HI]]]
(Even before this patch the final close bracket did not need to be
wrapped in {{}}, but people tended to do it anyway for symmetry.)
This does not introduce any ambiguity since "[[" was always followed by
an identifier or '@' or '#', so "[[[" was always an error.
I've included a few test updates in this patch just for illustration and
testing. There are a couple of hundred tests that could be updated as a
follow up, mostly in test/CodeGen/.
Differential Revision: https://reviews.llvm.org/D117117
Change-Id: Ia6bc6f65cb69734821c911f54a43fe1c673bcca7
Added:
Modified:
llvm/lib/FileCheck/FileCheck.cpp
llvm/test/CodeGen/Mips/msa/3r-s.ll
llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
llvm/test/FileCheck/regex-brackets.txt
Removed:
################################################################################
diff --git a/llvm/lib/FileCheck/FileCheck.cpp b/llvm/lib/FileCheck/FileCheck.cpp
index 5238627386d41..6186af444e736 100644
--- a/llvm/lib/FileCheck/FileCheck.cpp
+++ b/llvm/lib/FileCheck/FileCheck.cpp
@@ -1007,8 +1007,9 @@ bool Pattern::parsePattern(StringRef PatternStr, StringRef Prefix,
// brackets. They also accept a combined form which sets a numeric variable
// to the evaluation of an expression. Both string and numeric variable
// names must satisfy the regular expression "[a-zA-Z_][0-9a-zA-Z_]*" to be
- // valid, as this helps catch some common errors.
- if (PatternStr.startswith("[[")) {
+ // valid, as this helps catch some common errors. If there are extra '['s
+ // before the "[[", treat them literally.
+ if (PatternStr.startswith("[[") && !PatternStr.startswith("[[[")) {
StringRef UnparsedPatternStr = PatternStr.substr(2);
// Find the closing bracket pair ending the match. End is going to be an
// offset relative to the beginning of the match string.
@@ -1183,12 +1184,14 @@ bool Pattern::parsePattern(StringRef PatternStr, StringRef Prefix,
Substitutions.push_back(Substitution);
}
}
+
+ continue;
}
// Handle fixed string matches.
// Find the end, which is the start of the next regex.
- size_t FixedMatchEnd = PatternStr.find("{{");
- FixedMatchEnd = std::min(FixedMatchEnd, PatternStr.find("[["));
+ size_t FixedMatchEnd =
+ std::min(PatternStr.find("{{", 1), PatternStr.find("[[", 1));
RegExStr += Regex::escape(PatternStr.substr(0, FixedMatchEnd));
PatternStr = PatternStr.substr(FixedMatchEnd);
}
diff --git a/llvm/test/CodeGen/Mips/msa/3r-s.ll b/llvm/test/CodeGen/Mips/msa/3r-s.ll
index a0521b80e53c4..5df1b826935b9 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-s.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-s.ll
@@ -28,7 +28,7 @@ declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>, i32) nounwind
; CHECK-DAG: ld.b [[WD:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R2]])
; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]])
-; CHECK-DAG: sld.b [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
+; CHECK-DAG: sld.b [[WD]], [[WS]][[[RT]]]
; CHECK-DAG: st.b [[WD]]
; CHECK: .size llvm_mips_sld_b_test
;
@@ -56,7 +56,7 @@ declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>, i32) nounwind
; CHECK-DAG: ld.h [[WD:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R2]])
; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]])
-; CHECK-DAG: sld.h [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
+; CHECK-DAG: sld.h [[WD]], [[WS]][[[RT]]]
; CHECK-DAG: st.h [[WD]]
; CHECK: .size llvm_mips_sld_h_test
;
@@ -84,7 +84,7 @@ declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>, i32) nounwind
; CHECK-DAG: ld.w [[WD:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R2]])
; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]])
-; CHECK-DAG: sld.w [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
+; CHECK-DAG: sld.w [[WD]], [[WS]][[[RT]]]
; CHECK-DAG: st.w [[WD]]
; CHECK: .size llvm_mips_sld_w_test
;
@@ -112,7 +112,7 @@ declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, <2 x i64>, i32) nounwind
; CHECK-DAG: ld.d [[WD:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R2]])
; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]])
-; CHECK-DAG: sld.d [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
+; CHECK-DAG: sld.d [[WD]], [[WS]][[[RT]]]
; CHECK-DAG: st.d [[WD]]
; CHECK: .size llvm_mips_sld_d_test
;
diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
index 0f092ad8c511c..5b87dc8307c45 100644
--- a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
+++ b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
@@ -196,7 +196,7 @@ define float @extract_v4f32_vidx() nounwind {
; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <4 x float> %2, i32 %3
- ; ALL-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
+ ; ALL-DAG: splat.w $w0, [[R1]][[[IDX]]]
ret float %4
}
@@ -262,7 +262,7 @@ define double @extract_v2f64_vidx() nounwind {
; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <2 x double> %2, i32 %3
- ; ALL-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
+ ; ALL-DAG: splat.d $w0, [[R1]][[[IDX]]]
ret double %4
}
@@ -317,10 +317,10 @@ define void @insert_v4f32_vidx(float %a) nounwind {
%3 = insertelement <4 x float> %1, float %a, i32 %2
; float argument passed in $f12
; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
- ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+ ; ALL-DAG: sld.b [[R1]], [[R1]][[[BIDX]]]
; ALL-DAG: insve.w [[R1]][0], $w12[0]
; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
- ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+ ; ALL-DAG: sld.b [[R1]], [[R1]][[[NIDX]]]
store <4 x float> %3, <4 x float>* @v4f32
; ALL-DAG: st.w [[R1]]
@@ -346,10 +346,10 @@ define void @insert_v2f64_vidx(double %a) nounwind {
%3 = insertelement <2 x double> %1, double %a, i32 %2
; double argument passed in $f12
; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
- ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+ ; ALL-DAG: sld.b [[R1]], [[R1]][[[BIDX]]]
; ALL-DAG: insve.d [[R1]][0], $w12[0]
; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
- ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+ ; ALL-DAG: sld.b [[R1]], [[R1]][[[NIDX]]]
store <2 x double> %3, <2 x double>* @v2f64
; ALL-DAG: st.d [[R1]]
diff --git a/llvm/test/FileCheck/regex-brackets.txt b/llvm/test/FileCheck/regex-brackets.txt
index fd8568d3a504f..27ddf98d420a8 100644
--- a/llvm/test/FileCheck/regex-brackets.txt
+++ b/llvm/test/FileCheck/regex-brackets.txt
@@ -2,6 +2,7 @@
op r1
op r2, [x r1]
+op r3, [r1]
; CHECK: op [[REG:r[0-9]]]
; CHECK: op [[REG2:r[0-9]]], [x [[REG]]]
-
+; CHECK: op [[REG3:r[0-9]]], [[[REG]]]
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