[PATCH] D114405: Optimize shift and accumulate pattern in AArch64.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks. Looks good, as far as I can tell.

Can you make sure there are some i64 tests, especially v1i64. Those have a different tablegen class, so it would be good to make sure they have tests covering them.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1800-1804
+    KnownBits Known2, Known3;
+    Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
+    Known3 = DAG.computeKnownBits(Op->getOperand(2), Depth + 1);
+    if (!Known2.isConstant() || !Known3.isConstant())
+      break;
----------------
Is this chunk needed?  I think the operands should be constants by definition.


================
Comment at: llvm/test/CodeGen/AArch64/shift-accumulate.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+
----------------
I tend to use -mtriple=aarch64-none-eabi


================
Comment at: llvm/test/CodeGen/AArch64/shift-accumulate.ll:4
+
+define dso_local <4 x i16> @usra_v4i16(<8 x i8> %0) local_unnamed_addr #0 align 32 {
+; CHECK-LABEL: usra_v4i16:
----------------
You can usually remove dso_local and local_unnamed_addr #0 align 32, to make the tests a little cleaner.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D114405/new/

https://reviews.llvm.org/D114405