[PATCH] D116677: [2/4] [MC][NFC] Add an optional PreviousInst argument to MCInstrAnalysis::evaluateBranch

[Fangrui Song via Phabricator via llvm-commits]

MaskRay added a comment.

Checking the consecutive pair of instructions likely works for the majority of cases for some architectures. It fails when a RISC architecture interleaves the high and low parts with an unrelated instruction. This pattern is pretty common on AArch64.
Ideally that case should be handled as well.

  % cat a.c
  int a, b;
  int foo() { return a + b; }
  % clang --target=aarch64-linux-gnu -nostdlib -fuse-ld=lld -O1 a.c -o a
  % llvm-objdump -d a
  ...
  000000000021022c <foo>:
    21022c: 88 00 00 90   adrp    x8, 0x220000 <foo+0x40>
    210230: 89 00 00 90   adrp    x9, 0x220000 <foo+0x44>
    210234: 08 45 42 b9   ldr     w8, [x8, #580]
    210238: 29 49 42 b9   ldr     w9, [x9, #584]
    21023c: 20 01 08 0b   add     w0, w9, w8
    210240: c0 03 5f d6   ret

To obtain the addresses of a and b, we need to have states, which can be in MCInstrAnalysis itself.
llvm-objdump output is a disassembly dead listing. It is not a recursive disassembler and there is no basic block information.
So something may be fundamentally difficult to do, e.g. we may not reliably clear states when a new instruction is at the start of a new basic block...


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  https://reviews.llvm.org/D116677/new/

https://reviews.llvm.org/D116677