[llvm] 15a78f9 - [RISCV] Remove stale references to experimental-b. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 12 12:17:26 PST 2022
Author: Craig Topper
Date: 2022-01-12T12:13:21-08:00
New Revision: 15a78f9d09e2406d81cb26a5a40d25ef6b54f4e1
URL: https://github.com/llvm/llvm-project/commit/15a78f9d09e2406d81cb26a5a40d25ef6b54f4e1
DIFF: https://github.com/llvm/llvm-project/commit/15a78f9d09e2406d81cb26a5a40d25ef6b54f4e1.diff
LOG: [RISCV] Remove stale references to experimental-b. NFC
Differential Revision: https://reviews.llvm.org/D117136
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
llvm/test/CodeGen/RISCV/rv32zbb.ll
llvm/test/CodeGen/RISCV/rv32zbp.ll
llvm/test/CodeGen/RISCV/rv32zbs.ll
llvm/test/CodeGen/RISCV/rv32zbt.ll
llvm/test/MC/RISCV/rv32zba-invalid.s
llvm/test/MC/RISCV/rv32zbb-invalid.s
llvm/test/MC/RISCV/rv32zbbp-invalid.s
llvm/test/MC/RISCV/rv32zbc-invalid.s
llvm/test/MC/RISCV/rv32zbe-invalid.s
llvm/test/MC/RISCV/rv32zbf-invalid.s
llvm/test/MC/RISCV/rv32zbp-invalid.s
llvm/test/MC/RISCV/rv32zbr-invalid.s
llvm/test/MC/RISCV/rv32zbs-invalid.s
llvm/test/MC/RISCV/rv32zbt-invalid.s
llvm/test/MC/RISCV/rv64zba-invalid.s
llvm/test/MC/RISCV/rv64zbb-invalid.s
llvm/test/MC/RISCV/rv64zbbp-invalid.s
llvm/test/MC/RISCV/rv64zbe-invalid.s
llvm/test/MC/RISCV/rv64zbf-invalid.s
llvm/test/MC/RISCV/rv64zbm-invalid.s
llvm/test/MC/RISCV/rv64zbp-invalid.s
llvm/test/MC/RISCV/rv64zbr-invalid.s
llvm/test/MC/RISCV/rv64zbt-invalid.s
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
index e0d3c8f423825..aab1817aff782 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
@@ -168,8 +168,8 @@ define i32 @rol_i32(i32 %a, i32 %b) nounwind {
ret i32 %or
}
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
declare i64 @llvm.fshl.i64(i64, i64, i64)
@@ -276,8 +276,8 @@ define i32 @ror_i32(i32 %a, i32 %b) nounwind {
ret i32 %or
}
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
declare i64 @llvm.fshr.i64(i64, i64, i64)
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll
index 8a6b3d20c3833..f4e5efaaa36d9 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll
@@ -502,8 +502,8 @@ define i32 @min_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
define i64 @min_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: min_i64:
@@ -563,8 +563,8 @@ define i32 @max_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
define i64 @max_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: max_i64:
@@ -624,8 +624,8 @@ define i32 @minu_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
define i64 @minu_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: minu_i64:
@@ -685,8 +685,8 @@ define i32 @maxu_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: maxu_i64:
diff --git a/llvm/test/CodeGen/RISCV/rv32zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbp.ll
index 481fa00a2f209..026a27b691196 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbp.ll
@@ -2854,8 +2854,8 @@ define i32 @pack_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
define i64 @pack_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: pack_i64:
@@ -2894,8 +2894,8 @@ define i32 @packu_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
define i64 @packu_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packu_i64:
diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll
index fada2e2cf1ae7..42fd06f94a662 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll
@@ -132,8 +132,8 @@ define signext i32 @bset_i32_zero(i32 signext %a) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
define i64 @bset_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: bset_i64:
@@ -211,8 +211,8 @@ define i32 @binv_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
define i64 @binv_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: binv_i64:
@@ -274,8 +274,8 @@ define i32 @bext_i32_no_mask(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
define i64 @bext_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: bext_i64:
diff --git a/llvm/test/CodeGen/RISCV/rv32zbt.ll b/llvm/test/CodeGen/RISCV/rv32zbt.ll
index 9cb081c1c70a7..1582b4f62265b 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbt.ll
@@ -332,8 +332,8 @@ define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet an efficient pattern-matching with bit manipulation
; instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions that can match more efficiently this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions that can match more efficiently this pattern.
declare i64 @llvm.fshl.i64(i64, i64, i64)
@@ -407,8 +407,8 @@ define i32 @fshr_i32(i32 %a, i32 %b, i32 %c) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet an efficient pattern-matching with bit manipulation
; instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions that can match more efficiently this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions that can match more efficiently this pattern.
declare i64 @llvm.fshr.i64(i64, i64, i64)
diff --git a/llvm/test/MC/RISCV/rv32zba-invalid.s b/llvm/test/MC/RISCV/rv32zba-invalid.s
index a059dc41f63ae..1c5e4ef828535 100644
--- a/llvm/test/MC/RISCV/rv32zba-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zba-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zba < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zba < %s 2>&1 | FileCheck %s
# Too few operands
sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbb-invalid.s b/llvm/test/MC/RISCV/rv32zbb-invalid.s
index 473207c49e6d3..1ef3c6fa8d5c3 100644
--- a/llvm/test/MC/RISCV/rv32zbb-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbb-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbb < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zbb < %s 2>&1 | FileCheck %s
# Too many operands
clz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbbp-invalid.s b/llvm/test/MC/RISCV/rv32zbbp-invalid.s
index 5f28c4dfc6108..b5f79cd594ff4 100644
--- a/llvm/test/MC/RISCV/rv32zbbp-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbbp-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbb,experimental-zbp < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zbb,+experimental-zbp < %s 2>&1 | FileCheck %s
# Too few operands
andn t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbc-invalid.s b/llvm/test/MC/RISCV/rv32zbc-invalid.s
index 144656aabbf02..044bf46307b02 100644
--- a/llvm/test/MC/RISCV/rv32zbc-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbc-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbc < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zbc < %s 2>&1 | FileCheck %s
# Too few operands
clmul t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbe-invalid.s b/llvm/test/MC/RISCV/rv32zbe-invalid.s
index 4d4124778f133..68431bc104d4e 100644
--- a/llvm/test/MC/RISCV/rv32zbe-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbe-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s
# Too few operands
bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbf-invalid.s b/llvm/test/MC/RISCV/rv32zbf-invalid.s
index c701e25598690..66d12fbbe5c21 100644
--- a/llvm/test/MC/RISCV/rv32zbf-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbf-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbf < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s
# Too few operands
bfp t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbp-invalid.s b/llvm/test/MC/RISCV/rv32zbp-invalid.s
index 11e7e83383778..b0943ea94dd5b 100644
--- a/llvm/test/MC/RISCV/rv32zbp-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbp-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbp < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbp < %s 2>&1 | FileCheck %s
# Too few operands
gorc t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbr-invalid.s b/llvm/test/MC/RISCV/rv32zbr-invalid.s
index 9a6a6b5fbf40c..90e3a2c1ab001 100644
--- a/llvm/test/MC/RISCV/rv32zbr-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbr-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s
# Too many operands
crc32.b t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbs-invalid.s b/llvm/test/MC/RISCV/rv32zbs-invalid.s
index b5a6f2775ce6f..b18ecb3e82121 100644
--- a/llvm/test/MC/RISCV/rv32zbs-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbs-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbs < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zbs < %s 2>&1 | FileCheck %s
# Too few operands
bclr t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbt-invalid.s b/llvm/test/MC/RISCV/rv32zbt-invalid.s
index 2d81463572f72..101a531faa42c 100644
--- a/llvm/test/MC/RISCV/rv32zbt-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbt-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbt < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbt < %s 2>&1 | FileCheck %s
# Too few operands
cmix t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64zba-invalid.s b/llvm/test/MC/RISCV/rv64zba-invalid.s
index 70495002e6b97..358d8b3a6e11f 100644
--- a/llvm/test/MC/RISCV/rv64zba-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zba-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zba < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zba < %s 2>&1 | FileCheck %s
# Too few operands
slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbb-invalid.s b/llvm/test/MC/RISCV/rv64zbb-invalid.s
index cb5c3bbef022e..28efc0fd95e82 100644
--- a/llvm/test/MC/RISCV/rv64zbb-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbb-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zbb < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zbb < %s 2>&1 | FileCheck %s
# Too many operands
clzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbbp-invalid.s b/llvm/test/MC/RISCV/rv64zbbp-invalid.s
index a71b5c27d1957..a8c1d4746cd13 100644
--- a/llvm/test/MC/RISCV/rv64zbbp-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbbp-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zbb,experimental-zbp < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zbb,+experimental-zbp < %s 2>&1 | FileCheck %s
# Too few operands
rolw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbe-invalid.s b/llvm/test/MC/RISCV/rv64zbe-invalid.s
index 00c9001f39d9f..003f421fc5eb9 100644
--- a/llvm/test/MC/RISCV/rv64zbe-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbe-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s
# Too few operands
bdecompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbf-invalid.s b/llvm/test/MC/RISCV/rv64zbf-invalid.s
index 0eb91cf0c0a91..97ea8a97f2ff3 100644
--- a/llvm/test/MC/RISCV/rv64zbf-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbf-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbf < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s
# Too few operands
bfpw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbm-invalid.s b/llvm/test/MC/RISCV/rv64zbm-invalid.s
index 2a750074896c5..ef7800169e9b9 100644
--- a/llvm/test/MC/RISCV/rv64zbm-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbm-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbm < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbm < %s 2>&1 | FileCheck %s
# Too many operands
bmatflip t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbp-invalid.s b/llvm/test/MC/RISCV/rv64zbp-invalid.s
index d5b37b2f8dab4..9a56c9243b99e 100644
--- a/llvm/test/MC/RISCV/rv64zbp-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbp-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbp < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbp < %s 2>&1 | FileCheck %s
# Too few operands
gorcw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbr-invalid.s b/llvm/test/MC/RISCV/rv64zbr-invalid.s
index a5e6897c25303..ee383d46af6b3 100644
--- a/llvm/test/MC/RISCV/rv64zbr-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbr-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s
# Too many operands
crc32.d t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbt-invalid.s b/llvm/test/MC/RISCV/rv64zbt-invalid.s
index 57f36b9af30c1..c669176985eb5 100644
--- a/llvm/test/MC/RISCV/rv64zbt-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbt-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbt < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbt < %s 2>&1 | FileCheck %s
# Too few operands
fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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