[PATCH] D117118: [NVPTX] Fix shr/and pair replace with bfe

[Aidan Belton via Phabricator via llvm-commits]

AidanBeltonS created this revision.
Herald added subscribers: asavonic, hiraditya, jholewinski.
AidanBeltonS requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This PR changes the types of two unsigned 64-bit ints to signed 64-bit ints. 
This fixes an issue where `GoodBits` should be a negative value, however due to the type being unsigned it becomes a very large positive number.
The replacement causes a bug where shr/and pairs are incorrectly replaced with bfe. Despite the shr shifting all values to become the same value as the signed bit.

Two checks are added to test that the correct behaviour with too large shifts is occurring.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117118

Files:
  llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
  llvm/test/CodeGen/NVPTX/bfe.ll


Index: llvm/test/CodeGen/NVPTX/bfe.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/bfe.ll
+++ llvm/test/CodeGen/NVPTX/bfe.ll
@@ -30,3 +30,23 @@
   %val1 = and i32 %val0, 7
   ret i32 %val1
 }
+
+; CHECK: bfe3
+define i32 @bfe3(i32 %a) {
+; CHECK-NOT: bfe %r{{[0-9]+}}, %r{{[0-9]+}}, 31, 4
+; CHECK: shr
+; CHECK: and
+  %val0 = ashr i32 %a, 31
+  %val1 = and i32 %val0, 15
+  ret i32 %val1
+}
+
+; CHECK: bfe4
+define i64 @bfe4(i64 %a) {
+; CHECK-NOT: bfe %r{{[0-9]+}}, %r{{[0-9]+}}, 63, 3
+; CHECK: shr
+; CHECK: and
+  %val0 = ashr i64 %a, 63
+  %val1 = and i64 %val0, 7
+  ret i64 %val1
+}
Index: llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -3405,7 +3405,7 @@
     }
 
     // How many bits are in our mask?
-    uint64_t NumBits = countTrailingOnes(MaskVal);
+    int64_t NumBits = countTrailingOnes(MaskVal);
     Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
 
     if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
@@ -3417,7 +3417,7 @@
         uint64_t StartVal = StartConst->getZExtValue();
         // How many "good" bits do we have left?  "good" is defined here as bits
         // that exist in the original value, not shifted in.
-        uint64_t GoodBits = Start.getValueSizeInBits() - StartVal;
+        int64_t GoodBits = Start.getValueSizeInBits() - StartVal;
         if (NumBits > GoodBits) {
           // Do not handle the case where bits have been shifted in. In theory
           // we could handle this, but the cost is likely higher than just


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D117118.399326.patch
Type: text/x-patch
Size: 1715 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220112/0349ff79/attachment.bin>