[PATCH] D117109: [LoopVectorize][AArch64] Use get.active.lane.mask intrinsic when SVE is enabled

[David Sherwood via Phabricator via llvm-commits]

david-arm created this revision.
david-arm added reviewers: sdesmalen, kmclaughlin, dmgreen, fhahn, peterwaller-arm.
Herald added subscribers: ctetreau, CarolineConcatto, rogfer01, hiraditya, kristof.beyls, tschuett.
david-arm requested review of this revision.
Herald added subscribers: llvm-commits, vkmr.
Herald added a project: LLVM.

When SVE is enabled for AArch64 targets it makes more sense to use the
get.active.lane.mask intrinsic, because SVE has an exact 1-1 mapping
from the intrinsic to the 'whilelo' instruction for legal vector types.
This instruction neatly takes overflow into account as well. This patch
fixes an issue in VPInstruction::generateInstruction that assumed we are
only dealing with fixed-width vectors.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117109

Files:
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/lib/Transforms/Vectorize/VPlan.cpp
  llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
  llvm/test/Transforms/LoopVectorize/AArch64/tail-fold-uniform-memops.ll

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