[PATCH] D116308: [Huawei][Allocator] Fix the spill of status register nzcv

Tue Jan 11 00:38:50 PST 2022

dmgreen added inline comments.

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Comment at: llvm/test/CodeGen/MIR/AArch64/greedy-spill-nzcv.mir:25
+    ; CHECK-NEXT: STRXui $nzcv, [[STACK1:%.*]], 0 :: (store (s64) into [[STACK1]])
+    ; CHECK: $nzcv = LDRXui [[STACK1]], 0 :: (load (s64) from [[STACK1]])
+    %l.addr.i4 = alloca i64, align 8
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My point is that this isn't a valid instruction (I'm pretty sure, correct me if I'm wrong). There is no AArch64 instruction that loads nzcv directly from the stack.

I think we need to stop the code from getting to this point, by preventing the DAG Combine from making overlapping nzcv ranges, in this case by producing two CCMPWi's for each of the places that they get used.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116308/new/

https://reviews.llvm.org/D116308