[PATCH] D116877: [GlobalISel] Fix a big-endian-related bug in CallLowering

[Sheng via Phabricator via llvm-commits]

0x59616e updated this revision to Diff 398826.
0x59616e added a comment.

update diff according to @arsenm suggestion


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116877/new/

https://reviews.llvm.org/D116877

Files:
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/test/CodeGen/M68k/GlobalISel/c-call.ll
  llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll


Index: llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
===================================================================
--- llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
+++ llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
@@ -206,8 +206,8 @@
   ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
   ; CHECK:   [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
   ; CHECK:   [[G_UNMERGE_VAL1:%[0-9]+]]:_(s32), [[G_UNMERGE_VAL2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[G_MERGE_VAL]](s64)
-  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL1]](s32)
-  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL2]](s32)
-  ; CHECK:   RTS implicit $d0, implicit $d1
+  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL1]](s32)
+  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL2]](s32)
+  ; CHECK:   RTS implicit $d1, implicit $d0
   ret i64 %a
 }
Index: llvm/test/CodeGen/M68k/GlobalISel/c-call.ll
===================================================================
--- llvm/test/CodeGen/M68k/GlobalISel/c-call.ll
+++ llvm/test/CodeGen/M68k/GlobalISel/c-call.ll
@@ -43,4 +43,33 @@
   %3 = call i32 @callee3(i32 %0, i32 %1)
   ret i32 %3
 }
-declare i32 @callee3(i32, i32)
\ No newline at end of file
+declare i32 @callee3(i32, i32)
+
+define i64 @test_ret_i64(i64 %0) nounwind {
+; CHECK-LABEL: test_ret_i64:
+; CHECK:       ; %bb.0
+; CHECK-NEXT:  move.l (8,%sp), %d1
+; CHECK-NEXT:  move.l (4,%sp), %d0
+; CHECK-NEXT:  rts
+  ret i64 %0
+}
+
+define void @test_passing_i64(i64 %0, i64 %1) nounwind {
+; CHECK-LABEL: test_passing_i64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:  suba.l  #20, %sp
+; CHECK-NEXT:  move.l (28,%sp), %d0
+; CHECK-NEXT:  move.l (24,%sp), %d1
+; CHECK-NEXT:  move.l (36,%sp), %a0
+; CHECK-NEXT:  move.l (32,%sp), %a1
+; CHECK-NEXT:  move.l %a0, (4,%sp)
+; CHECK-NEXT:  move.l %a1, (0,%sp)
+; CHECK-NEXT:  move.l %d0, (12,%sp)
+; CHECK-NEXT:  move.l %d1, (8,%sp)
+; CHECK-NEXT:  jsr callee_test_passing_i64
+; CHECK-NEXT:  adda.l #20, %sp
+; CHECK-NEXT:  rts
+  call void @callee_test_passing_i64(i64 %1, i64 %0)
+  ret void
+}
+declare void @callee_test_passing_i64(i64, i64)
Index: llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -674,10 +674,12 @@
                       ValTy, extendOpFromFlags(Args[i].Flags[0]));
     }
 
+    bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
     for (unsigned Part = 0; Part < NumParts; ++Part) {
       Register ArgReg = Args[i].Regs[Part];
       // There should be Regs.size() ArgLocs per argument.
-      VA = ArgLocs[j + Part];
+      unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
+      CCValAssign &VA = ArgLocs[j + Idx];
       const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
 
       if (VA.isMemLoc() && !Flags.isByVal()) {


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