[PATCH] D116720: [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled

[Ben Shi via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbd653f6406e7: [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled (authored by Luhaocong, committed by benshi001).

Changed prior to commit:
  https://reviews.llvm.org/D116720?vs=398584&id=398806#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116720/new/

https://reviews.llvm.org/D116720

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/alu16.ll
  llvm/test/CodeGen/RISCV/and.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/calling-conv-half.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/div.ll
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-intrinsics.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/float-intrinsics.ll
  llvm/test/CodeGen/RISCV/half-arith.ll
  llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/half-convert-strict.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-intrinsics.ll
  llvm/test/CodeGen/RISCV/rem.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbs.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbs.ll
  llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
  llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

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