[PATCH] D116771: [RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

LGTM, modulo one comment.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7058
+
+  // Don't do this for f16 with Zfhmin and not Zfh.
+  if (Src.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh())
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Is it possible to add some test coverage for this?


Repository:
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  https://reviews.llvm.org/D116771/new/

https://reviews.llvm.org/D116771