[PATCH] D116664: [AArch64] Improve codegen for get.active.lane.mask when SVE is available

[David Sherwood via Phabricator via llvm-commits]

david-arm added a comment.

In D116664#3223018 <https://reviews.llvm.org/D116664#3223018>, @efriedma wrote:

> I'm not sure the testcases actually illustrate the cases we care about.  Generally, I would expect the result of llvm.get.active.lane.mask() to be used in a select instruction, or a masked load, or something like that.  And in that case, I'm not sure the way you're choosing the VT is appropriate; the instruction using the mask is probably not going to expect a 64-bit vector.

Hi @efriedma, I think these testcases are still useful by themselves because they are succint and make it easy to see how one IR instruction maps to assembly. At the moment if I add more complex test cases involving a select, for example, the code quality ends up being awful regardless of what promoted VT I choose. I think there is a still a codegen issue somewhere because I see loads of pointless lane moves whenever I add something like a select. So for now, I'd like to leave the tests as they are.

However, I do take your point about trying to second guess how the masks are going to be used, and perhaps I can make the choice of promoted VT simpler for now, and leave the `xtn` instructions in.


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