[PATCH] D116737: [DAG][AArch64][SVE] Fix VLS mulh code generation

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Yes, that was what I was thinking, because it seemed odd that such a constant representation exists by this point in the pipeline.  However, I can see that it's coming from the test itself and so I've changed my mind and am now wondering if there actually a problem that needs solving here?

The tests are using a non-standard immediate representation (aka "fixed vector shuffle of an inserted constant") that LLVM would have converted to a constant vector (aka `<i16 8, i16 8,....`) long before it get's to the code generator.  This is backed up by running the test through clang, which results in `smul` when expected.

This makes me think that to protect the `MULS/MULU` functionality, you just need to update the test itself to remove the non-standard representation.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D116737/new/

https://reviews.llvm.org/D116737